參數(shù)資料
型號： AD8522
廠商： Analog Devices, Inc.
英文描述： +5 Volt, Serial Input,Dual 12-Bit DAC(串行輸入,雙12位D/A轉(zhuǎn)換器)
中文描述： 5伏，串行輸入，雙12位DAC（串行輸入，雙12位的D / A轉(zhuǎn)換器）
文件頁數(shù)： 2/8頁
文件大小： 189K
代理商： AD8522
AD8522–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
T yp
Max
Units
ST AT IC PERFORMANCE
Resolution
1
Relative Accuracy
Differential Nonlinearity
Zero-Scale Error
Full-Scale Voltage
2
Full-Scale T empco
2, 3
MAT CHING PERFORMANCE
Linearity Matching Error
ANALOG OUT PUT
Output Current
Load Regulation at Half-Scale
Capacitive Load
3
REFERENCE OUT PUT
Output Voltage
Output Source Current
4
Line Rejection
Load Regulation
LOGIC INPUT S & OUT PUT S
Logic Input Low Voltage
Logic Input High Voltage
Input Leakage Current
Input Capacitance
3
Logic Output Voltage Low
Logic Output Voltage High
T IMING SPECIFICAT IONS
3, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Clear Pulse Width
Load Setup
Load Hold
Select
Deselect
Clock to SDO Propagation Delay
AC CHARACT ERIST ICS
3, 5
Voltage Output Settling T ime
6
Crosstalk
N
INL
DNL
V
ZSE
V
FS
T CV
FS
12
-1.5
-1
Bits
LSB
LSB
mV
Volts
ppm/
°
C
±
0.5
±
0.5
+0.5
4.095
±
15
+1.5
+1
+3
4.111
Monotonic
Data = 000
H
Data = FFF
H
4.079
V
FS
A/B
±
1
LSB
I
OUT
LD
REG
C
L
Data = 800
H
,
V
OUT
≤
3 LSB
R
L
= 402
to
∞
, Data = 800
H
No Oscillation
±
5
3
mA
LSB
pF
1
500
V
REF
I
REF
LN
REJ
LD
REG
2.484
2.500
2.516
5
0.08
0.1
V
mA
%/V
%/mA
V
REF
< 18 mV
0.025
0.025
I
REF
= 0 to 5 mA, Data = 800
H
V
IL
V
IH
I
IL
C
IL
V
OL
V
OH
0.8
V
V
μ
A
pF
V
V
2.4
10
10
0.4
I
OL
= 1.6 mA
I
OH
= 400
μ
A
3.5
t
CH
t
CL
t
LDW
t
DS
t
DH
t
CLRW
t
LD1
t
LD2
t
CSS
t
CSH
t
PD
35
35
25
10
20
20
10
10
30
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
45
80
t
S
C
T
T o
±
1 LSB of Final Value
Signal Measured at DAC Output,
While Changing Opposite
LDA
/
B
Half-Scale T ransition
Signal Measured at DAC Output,
While Changing Data Without
LDA
/
B
16
μ
s
38
13
dB
nV s
DAC Glitch
Digital Feedthrough
Q
D
FT
2
nV s
SUPPLY CHARACT ERIST ICS
Positive Supply Current
I
DD
V
DD
= 5.5 V, V
IH
= 2.4 V or V
IL
= 0.8 V
V
DD
= 5 V, V
IL
= 0 V
V
DD
= 5 V, V
IH
= 2.4 V or V
IL
= 0.8 V
V
DD
= 5 V, V
IL
= 0 V
V
DD
=
±
5%
3
1
15
5
0.002
5
2
25
10
0.004
mA
mA
mW
mW
%/%
Power Dissipation
7
P
DISS
Power Supply Sensitivity
PSS
NOT ES
1
1 LSB = 1 mV for 0 V to +4.095 V output range.
2
Includes internal voltage reference error.
3
T hese parameters are guaranteed by design and not subject to production testing.
4
Very little sink current is available at the V
REF
pin. Use external buffer if setting up a virtual ground.
5
All input control signals are specified with t
= t
= 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6
T he settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
7
Power Dissipation is calculated I
DD
×
5 V.
Specifications subject to change without notice.
(@ V
DD
= +5.0 V
6
10%, R
L
= No Load, –40
8
C
≤
T
A
≤
+85
8
C, both DACs tested, unless
otherwse noted)
REV. A
–2–
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