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參數(shù)資料
| 型號(hào)： | AD845KNZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大小： | 0K |
| 描述： | IC OPAMP JFET 16MHZ PREC 8DIP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 100 V/µs |
| 增益帶寬積： | 16MHz |
| 電流 - 輸入偏壓： | 500pA |
| 電壓 - 輸入偏移： | 100µV |
| 電流 - 電源： | 10mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 18 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁(yè)面： | 766 (CN2011-ZH PDF) |
AD845
REV. E
–7–
MEASURING AD845 SETTLING TIME
Figure 1 shows AD845 settling time performance. This measure-
ment was accomplished by driving the amplifier in the unity
gain inverting mode with a fast pulse generator. The input
summing junction was measured using false nulling techniques.
Settling time is defined as the interval of time from the application
of an ideal step function input until the closed-loop amplifier
output has entered and remains within a specified error band.
Components of settling time include:
1. Propagation time through the amplifier
2. Slewing time to approach the final output value
3. Recovery time from overload associated with the slewing
4. Linear settling to within a specified error band
These individual components can be seen easily in Figure 1.
Settling time is extremely important in high speed applications
where the current output of a DAC must be converted to a
voltage. When driving a 500
W load in parallel with a 100 pF
capacitor, the AD845 settles to 0.1% in 250 ns and to 0.01% in
310 ns.
Figure 1. Settling Characteristics 0 V to 10 V Step
Upper Trace: Output of AD845 Under Test (5 V/Div)
Lower Trace: Error Voltage (1 mV/Div)
Figure 2. Settling Time Test Circuit
A HIGH SPEED INSTRUMENTATION AMP
The 3-op amp instrumentation amplifier circuit shown in
Figure 3 can provide a range of gains from unity up to 1000 and
higher. The instrumentation amplifier configuration features
high common-mode rejection, balanced differential inputs, and
stable, accurately defined gain. Low input bias currents and fast
settling are achieved with the FET input AD845.
Most monolithic instrumentation amplifiers do not have the
high frequency performance of the circuit in Figure 3. The cir-
cuit bandwidth is 10.9 MHz at a gain of 1 and 8.8 MHz at a
gain of 10; settling time for the entire circuit is 900 ns to 0.01%
for a 10 V step (Gain = 10).
The capacitors employed in this circuit greatly improve the
amplifier’s settling time and phase margin.
Figure 3. High Performance, High Speed Instrumentation
Amplifier
Table I. Performance Summary for the 3-Op Amp
Instrumentation Amplifier Circuit
3-Op Amp In-Amp
Small Signal
Settling Time
Gain
RG
Bandwidth
to 0.01%
1Open
10.9 MHz
500 ns
22 k
W
8.8 MHz
500 ns
10
226
W
2.6 MHz
900 ns
100
20
W
290 kHz
7.5
ms
Note: Resistors around the amplifiers’ input pins need to be small enough in
value so that the RC time constant they form, with stray circuit capacitance,
does not reduce circuit bandwidth.
Figure 4. The Pulse Response of the 3-Op Amp
Instrumentation Amplifier. Gain = 1, Horizontal Scale =
0.5 ms/Div and Vertical Scale = 5 V/Div.
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