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參數(shù)資料
| 型號(hào)： | AD8401 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 8-Bit, 4-Channel Data Acquisition System(8位4通道DAS) |
| 中文描述： | 8位，4通道數(shù)據(jù)采集系統(tǒng)（4通道8位DAS）的 |
| 文件頁(yè)數(shù)： | 8/12頁(yè) |
| 文件大?。?/td> | 182K |
| 代理商： | AD8401 |
AD8401
–8–
REV. 0
An active low pulse, at any time, on the RESET pin asynchro-
nously forces all DAC register bits to zero. T he DAC output
voltage becomes zero volts and stays at that value until a new
data word is loaded into the DAC register with a new
WR
com-
mand. T he equivalent input logic for the DAC register loading
is shown in Figure 9.
RESET
CS
WR
DAC REGISTER
D0
D7
INPUT DATA
TO DAC LADDER
Figure 9. Equivalent DAC Register Control Logic
T Y PICAL PE RFORMANCE CHARACT E RIST ICS
1.0
–0.1
256
–0.5
0
0
0.5
192
128
64
DIGITAL INPUT CODE – DECIMAL
V
DD
= +5V
T
A
= +25
°
C
L
Figure 10. ADC Linearity Error vs. Digital Code
1.0
–0.1
256
–0.5
0
0
0.5
192
128
64
DIGITAL INPUT CODE – DECIMAL
V
DD
= +5V
T
A
= +25
°
C
L
Figure 11. DAC Linearity Error vs. Digital Code
120
0
–4.5
4.5
30
10
–3.5
20
60
40
50
70
80
90
110
100
3.5
2.5
1.5
0.5
–0.5
–1.5
FULL SCALE ERROR – LSB
–2.5
U
SS = 300 UNITS
T
A
= +25
°
C
Figure 12. ADC Full-Scale Error Histogram
2.5
–3.0
–1.5
–2.5
–2.0
0
–1.0
–0.5
0.5
1.0
1.5
2.0
100
–25
–50
75
50
25
0
TEMPERATURE –
°
C
A
V
DD
= +5V
Figure 13. ADC Full-Scale Error vs. Temperature
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相關(guān)代理商/技術(shù)參數(shù) |
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