參數(shù)資料
型號(hào)： AD8400ARZ1-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 16/32頁(yè)
文件大?。?/td> 0K
描述： IC POT DGTL 8BIT SGL 1K 8SOIC
標(biāo)準(zhǔn)包裝： 2,500
接片： 256
電阻（歐姆）： 1k
電路數(shù)： 1
溫度系數(shù)： 標(biāo)準(zhǔn)值 500 ppm/°C
存儲(chǔ)器類型： 易失
接口： 3 線 SPI（芯片選擇）
電源電壓： 2.7 V ~ 5.5 V
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SO
包裝： 帶卷 (TR)
AD8400/AD8402/AD8403
Rev. E | Page 23 of 32
1k
Ω
DIGITAL
PINS
LOGIC
01
09
2-
05
0
Figure 51. Equivalent ESD Protection Circuits
20
Ω
A,B,W
01
09
2
-05
1
Figure 52. Equivalent ESD Protection Circuit (Analog Pins)
A
CA
CB
W
RDAC
10k
Ω
B
CW
120pF
CA = 90.4pF (DW/256) + 30pF
CB = 90.4pF [1 – (DW/256)] + 30pF
01
09
2-
05
2
Figure 53. RDAC Circuit Simulation Model for RDAC = 10 kΩ
The AC characteristics of the RDAC are dominated by the
internal parasitic capacitances and the external capacitive loads.
The 3 dB bandwidth of the AD8403AN10 (10 kΩ resistor)
measures 600 kHz at half scale as a potentiometer divider.
Figure 30 provides the large signal Bode plot characteristics
of the three available resistor versions 10 kΩ, 50 kΩ, and 100 kΩ.
The gain flatness vs. frequency graph of the 1 kΩ version predicts
filter applications performance (see Figure 33). A parasitic
simulation model has been developed and is shown in Figure 53.
Listing I provides a macro model net list for the 10 kΩ RDAC.
Listing I. Macro Model Net List for RDAC
.PARAM DW=255, RDAC=10E3
*
.SUBCKT DPOT (A,W,)
*
CA A 0 {DW/256*90.4E-12+30E-12}
RAW A W {(1-DW/256)*RDAC+50}
CW W 0 120E-12
RBW W B {DW/256*RDAC+50}
CB B 0 {(1-DW/256)*90.4E-12+30E-12}
*
.ENDS DPOT
The total harmonic distortion plus noise (THD + N), shown in
Figure 41, is measured at 0.003% in an inverting op amp circuit
using an offset ground and a rail-to-rail OP279 amplifier.
Thermal noise is primarily Johnson noise, typically 9 nV/√Hz
for the 10 kΩ version at f = 1 kHz. For the 100 kΩ device,
thermal noise becomes 29 nV/√Hz. Channel-to-channel
crosstalk measures less than 65 dB at f = 100 kHz. To achieve
this isolation, the extra ground pins provided on the package to
segregate the individual RDACs must be connected to circuit
ground. AGND and DGND pins should be at the same voltage
potential. Any unused potentiometers in a package should be
connected to ground. Power supply rejection is typically 35 dB
at 10 kHz. Care is needed to minimize power supply ripple in
high accuracy applications.
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