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參數(shù)資料
| 型號： | AD8391AR-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC XDSL LINE DVR W/PWR DN 8-SOIC |
| 產(chǎn)品變化通告： | AD8391 Discontinuation 28/Feb/2012 |
| 標準包裝： | 1,000 |
| 類型： | 驅(qū)動器 |
| 驅(qū)動器/接收器數(shù)： | 2/0 |
| 規(guī)程： | xDSL |
| 電源電壓： | 3 V ~ 12 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
REV. A
AD8391
–12–
Evaluation Board
The AD8391 is available installed on an evaluation board.
Figure 10 shows the schematics for the evaluation board. AC-
coupling capacitors of 0.1
F, C6 and C11, in combination with
10 k
, resistors R25 and R26, will form a first-order high-pass
pole at 160 Hz.
The bill of materials included as Table III represents the com-
ponents that are installed in the evaluation board when it is
shipped to a customer. There are footprints for additional components,
such as an AD8138, that will convert a single-ended signal into a
differential signal. There is also a place for an AD9632, which can
be used to convert a differential signal into a single-ended signal.
Transformer Selection
Customer premise ADSL requires the transmission of a 13 dBm
(20 mW) DMT signal. The DMT signal has a crest factor of 5.3,
requiring the line driver to provide peak line power of 560 mW.
560 mW peak line power translates into a 7.5 V peak voltage on a
100
telephone line. Assuming that the maximum low distortion
output swing available from the AD8391 line driver on a 12 V
supply is 11 V, and taking into account the power lost due to the
termination resistance, a step-up transformer with a turns ratio
of 1:2 is adequate for most applications. If the modem designer
desires to transmit more than 13 dBm down the twisted pair, a
higher turns ratio can be used for the transformer. This trade-off
comes at the expense of higher power dissipation by the line
driver as well as increased attenuation of the downstream signal
that is received by the transceiver.
In the simplified differential drive circuit shown in Figure 6, the
AD8391 is coupled to the phone line through a step-up transformer
with a 1:2 turns ratio. R45 and R46 are back termination or line
matching resistors, each 12.5
[1/2 (100 /22)] where 100 is
the approximate phone line impedance. A transformer reflects
impedance from the line side to the IC side as a value inversely
proportional to the square of the turns ratio. The total differential
load for the AD8391, including the termination resistors, is 50
.
Even under these conditions, the AD8391 provides low distor-
tion signals to within 0.5 V of the power supply rails.
One must take care to minimize any capacitance present at the
outputs of a line driver. The sources of such capacitance can
include but are not limited to EMI suppression capacitors,
overvoltage protection devices, and the transformers used in the
hybrid. Transformers have two kinds of parasitic capacitances:
distributed or bulk capacitance and interwinding capacitance.
Distributed capacitance is a result of the capacitance created
between each adjacent winding on a transformer. Interwinding
capacitance is the capacitance that exists between the windings
on the primary and secondary sides of the transformer. The
existence of these capacitances is unavoidable and limiting both
distributed and interwinding capacitance to less than 20 pF each
should be sufficient for most applications.
It is also important that the transformer operates in its linear
region throughout the entire dynamic range of the driver.
Distortion introduced by the transformer can severely degrade
DSL performance, especially when operating at long loop lengths.
Using these calculations and a
θJA of 100°C/W for the SOIC,
Table II shows junction temperature versus power delivered to
the line for several supply voltages while operating at an ambient
temperature of 85
°C. Operation at a junction temperature over
the absolute maximum rating of 150
°C should be avoided.
Table II. Junction Temperature vs. Line Power
and Operating Voltage for SOIC at 85 C Ambient
VSUPPLY
PLINE, dBm
12
12.5
13
125
126
14
127
129
15
129
131
Thermal stitching, which connects the outer layers to the internal
ground plane(s), can help to use the thermal mass of the PCB to
draw heat away from the line driver and other active components.
Layout Considerations
As is the case with all high speed applications, careful attention
to printed circuit board layout details will prevent associated
board parasitics from becoming problematic. Proper RF design
techniques are mandatory. The PCB should have a ground plane
covering all unused portions of the component side of the board
to provide a low impedance return path. Removing the ground
plane on all layers from the areas near the input and output pins
will reduce stray capacitance, particularly in the area of the
inverting inputs. The signal routing should be short and direct in
order to minimize parasitic inductance and capacitance associated
with these traces. Termination resistors and loads should be located
as close as possible to their respective inputs and outputs.
Input and output traces should be kept as far apart as possible
to minimize coupling (crosstalk) through the board. Wherever
there are complementary signals, a symmetrical layout should be
provided to the extent possible to maximize balanced perfor-
mance. When running differential signals over a long distance, the
traces on the PCB should be close. This will reduce the radiated
energy and make the circuit less susceptible to RF interference.
Adherence to stripline design techniques for long signal traces
(greater than about one inch) is recommended.
AD8391
1
2
3
4
8
7
6
5
0.1 F
453
909
1 F
+
VIN
12.5
+–
+3V
453
909
1 F
–
VCC
12.5
0.1 F10 F
+
1:2
RL
–VS
+VS
VMID
Figure 6. Single-Supply Voltage Differential Drive Circuit
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