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參數(shù)資料
| 型號： | AD8383ACPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | Low Cost 10-Bit, 6-Channel Output Decimating LCD DecDriver |
| 中文描述： | LIQUID CRYSTAL DISPLAY DRIVER, QCC48 |
| 封裝： | 7 X 7 MM, 0.85 MM HEIGHT, MO-220VKKD-2, LFCSP-48 |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 376K |
| 代理商： | AD8383ACPZ |
AD8383
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 6 of 16
NC = NO CONNECT
AD8383
TOP VIEW
7mm
×
7mm
(Not to Scale)
NC
1
DB0
2
DB1
3
DB2
4
DB3
5
VID0
AVCC0,1
VID1
AGND1,2
VID2
36
35
34
33
32
DB4
6
DB5
7
DB6
8
DB7
9
DB8
10
AVCC2,3
VID3
AGND3,4
VID4
AVCC4,5
31
30
29
28
27
DB9
11
VID5
26
NC
12
AGND5
25
PIN 1
E
R
I
D
D
C
X
S
N
N
4
4
4
4
4
A
N
S
B
A
V
A
A
V
V
4
4
4
4
3
N
V
3
N
A
3
0
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin Name
Function
DB(0:9)
Data Input
Description
10-Bit Data Input. MSB = DB(0:9).
CLK
Clock
Clock Input.
STSQ
Start Sequence
The state of STSQ is detected on the active edge of CLK. A new data loading sequence begins on
the next active edge of CLK after STSQ is detected HIGH.
The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when E/O is
held LOW.
R/L
Right/Left Select
A new data loading sequence begins on the left with Channel 0 when this input is LOW, and on
the right with Channel 5 when this input is HIGH.
E/O
Even/Odd Select
The active CLK edge is the rising edge when this input is held HIGH and the falling edge when
this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is
HIGH and on the falling edges when this input is LOW.
XFR
Data Transfer
XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held HIGH.
Data is transferred to the video outputs on the next rising CLK edge after XFR is detected.
VID0–VID5
Analog Outputs
These pins are directly connected to the analog inputs of the LCD panel.
V1, V2
Reference Voltages
The voltage applied between these pins set the reference levels of the analog outputs.
VREFHI,
VREFLO
Full-Scale References
The voltage applied between these pins sets the full-scale output voltage.
INV
Invert
When this pin is HIGH, the analog output voltages are above VMID. When LOW, the analog
output voltages are below VMID. VMID is a hypothetical reference level set by the voltages
applied to V1 and V2. VMID is equal to (V1 + V2)/2.
DVCC
Digital Power Supply
Digital Power Supply.
DGND
Digital Supply Return
This pin is normally connected to the analog ground plane.
AVCCx
Analog Power Supplies
Analog Power Supplies.
AGNDx
Analog Supply Returns
Analog Supply Returns.
BYP
Bypass
A 0.1 μF capacitor connected between this pin and AGND ensures optimum settling time.
STBY
Standby
When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD8384 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 6-Channel Decimating LCD DecDriver-R with Level Shifters |
| AD8384ASVZ | 功能描述:IC DRIVER LCD 6CH 10BIT 80-TQFP RoHS:是 類別:集成電路 (IC) >> PMIC - 顯示器驅(qū)動器 系列:DecDriver™ 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 顯示器類型:真空熒光 (VF) 配置:5 x 7（矩陣） 接口:串行 數(shù)字或字符:- 電流 - 電源:3.5mA 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:16-QSOP 包裝:帶卷 (TR) |
| AD8385 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 12-Channel Decimating LCD DECDRIVER with Level Shifters |
| AD8385ASVZ | 制造商:Analog Devices 功能描述: |
| AD8386 | 制造商:AD 制造商全稱:Analog Devices 功能描述:10-Bit, 12-Channel Output Decimating LCD Driver |
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