參數(shù)資料
型號(hào)： AD8370AREZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 6/28頁(yè)
文件大?。?/td> 0K
描述： IC AMP VGA DIFF LN 16TSSOP
產(chǎn)品培訓(xùn)模塊： Differential Circuit Design Techniques for Communication Applications
標(biāo)準(zhǔn)包裝： 96
放大器類(lèi)型： 可變?cè)鲆?br>
電路數(shù)： 1
輸出類(lèi)型： 差分
轉(zhuǎn)換速率： 5750 V/ns
-3db帶寬： 750MHz
電流 - 輸入偏壓： 400pA
電流 - 電源： 79mA
電壓 - 電源，單路/雙路(±)： 3 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm）裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 16-TSSOP-EP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 775 (CN2011-ZH PDF)
AD8370
Data Sheet
Rev. B | Page 14 of 28
OUTPUT AMPLIFIER
The output impedance is approximately 100 differential and,
like the input preamplifier, this impedance is formed using
active circuit elements. See Figure 40 for a simplified schematic
of the output interface.
03692-
038
VCC/2
740
OPHI/OPLO
Figure 40. OPHI/OPLO Simplified Circuit
The gain of the output amplifier, and thus the AD8370 as a
whole, is load dependent. The following equation can be used to
predict the gain deviation of the AD8370 from that at 100 as
the load is varied.
LOAD
R
ion
GainDeviat
98
1
98
1
+
=
.
For example, if RLOAD is 1 k, the gain is a factor of 1.80 (5.12 dB)
above that at 100 , all other things being equal. If RLOAD is 50
, the gain is a factor of 0.669 (3.49 dB) below that at 100 .
DIGITAL INTERFACE AND TIMING
The digital control port uses a standard TTL interface. The 8-bit
control word is read in a serial fashion when the LTCH pin is
held low. The levels presented to the DATA pin are read on each
rising edge of the CLCK signal. Figure 41 illustrates the timing
diagram for the control interface. Minimum values for timing
parameters are presented in Table 4. Figure 42 is a simplified
schematic of the digital input pins.
DATA
(PIN 14)
CLCK
(PIN 13)
LTCH
(PIN 12)
TDS
TES
TEH
MSB
MSB-1 MSB-2 MSB-3
LSB
LSB+1
LSB+2
LSB+3
TCK
TPW
03692-039
Figure 41. Digital Timing Diagram
Table 4. Serial Programming Timing Parameters
Parameter
Min
Unit
Clock Pulse Width (TPW)
25
ns
Clock Period (TCK)
50
ns
Setup Time Data vs. Clock (TDS)
10
ns
Setup Time Latch vs. Clock (TES)
20
ns
Hold Time Latch vs. Clock (TEH)
10
ns
10
A
CLCK/DATA/LTCH/PWUP
03692-
040
Figure 42. Simplified Circuit for Digital Inputs
03692-
041
VCC/2
75
VOCM
Figure 43. Simplified Circuit for VOCM Output
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