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參數(shù)資料
| 型號： | AD8370-EVAL |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 運(yùn)動控制電子 |
| 英文描述： | LF to 750 MHz Digitally Controlled VGA |
| 中文描述： | LF到750兆赫數(shù)字控制VGA |
| 文件頁數(shù)： | 20/28頁 |
| 文件大小： | 1043K |
| 代理商： | AD8370-EVAL |
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AD8370
Rev. 0 | Page 20 of 28
V
S
R
S
2
R
S
R
L
R
S
2
R
L
2
R
L
2
27pF
V
S
R
S
= 120
R
L
= 1200
200nH
100nH
100nH
27pF
BALANCED
CONFIGURATION
DE-NORMALIZED
SINGLE-ENDED
EQUIVALENT
V
S
R
S
=
= 0.1
R
L
= 1
L
N
= 0.074H
C
N
14.814F
NORMALIZED
SINGLE-ENDED
EQUIVALENT
= 60
= 60
= 600
= 600
f
C
= 70MHz
f
C
= 1Hz
0
Figure 54. Second-Order Butterworth Low-Pass Filter Design Example
A complete design example is shown in Figure 56. The AD8370
is configured for single-ended-to-differential conversion with
the input terminated down to present a single-ended 75 input.
A sixth-order Chebyshev differential filter is used to interface
the output of the AD8370 to the input of the AD9430 170 MSPS
12-bit ADC. The filter minimizes aliasing effects and improves
harmonic distortion performance.
The input of the AD9430 is terminated with a 1.5 k resistor so
that the overall load presented to the filter network is ~1 k
.
The variable gain of the AD8370 extends the useable dynamic
range of the ADC. The measured intermodulation distortion of
the combination is presented in Figure 55 at 42 MHz.
–130
–120
–100
–60
–40
–20
–10
0
–80
–110
–70
–50
–30
–90
d
0
10
20
30
40
50
60
70
FREQUENCY (MHz)
0
Figure 55. FFT Plot of Two-Tone Intermodulation Distortion at
42 MHz for the Circuit in Figure 56
In Figure 55, the intermodulation products are comparable to
the noise floor of the ADC. The spurious-free dynamic range of
the combination is better than 66 dB for a 70 MHz measurement
bandwidth.
3 V OPERATION
It is possible to operate the AD8370 at voltages as low as 3 V
with only minor performance degradation. Table 6 gives typical
specifications for operation at 3 V.
Table 6.
Parameter
Ouptut IP3
P1dB
3 dB Bandwidth
IMD3
Typical (70 MHz, R
L
= 100 )
+23.5 dBm
+12.7 dBm
650 MHz (HG 127)
82 dBc (R
L
= 1 k)
AD8370
I
I
V
P
V
V
O
O
O
O
V
L
C
D
I
I
6
7
8
2
3
5
1
11
10
9
15
14
16
13
12
4
SERIAL CONTROL INTERFACE
FROM 75
Tx-LINE
0.1
μ
F
1nF
0.1
μ
F
+V
S
27pF
68nH
180nH
220nH
39pF
27pF
1.5k
68nH
180nH
220nH
25
25
C
AC
C
AC
100nF
100nF
C
AC
100nF
C
AC
100nF
R
S
120
0
V
IN
B
AD9430
V
IN
A
Figure 56. ADC Interface Example
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