參數(shù)資料
型號： AD8330-EVALZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/32頁
文件大?。?/td> 0K
描述： BOARD EVAL FOR AD8330
標(biāo)準(zhǔn)包裝： 1
每 IC 通道數(shù)： 1 - 單
放大器類型： 可變增益
輸出類型： 差分，滿擺幅
轉(zhuǎn)換速率： 1500 V/µs
-3db帶寬： 150MHz
工作溫度： -40°C ~ 85°C
電流供應(yīng)（主 IC）： 20mA
電壓 - 電源，單路/雙路(±)： 2.7 V ~ 6 V
板類型： 完全填充
已供物品： 板
已用 IC / 零件： AD8330
產(chǎn)品目錄頁面： 775 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD8330ACPZ-R7DKR-ND - IC AMP VGA 150MHZ LN LP 16LFCSP
AD8330ACPZ-R2-ND - IC AMP VGA 150MHZ LN LP 16LFCSP
AD8330ACPZ-RL-ND - IC AMP VGA 150MHZ LN LP 16LFCSP
AD8330ACPZ-R7CT-ND - IC AMP VGA 150MHZ LN LP 16LFCSP
AD8330ACPZ-R7TR-ND - IC AMP VGA 150MHZ LN LP 16LFCSP
AD8330ARQZ-RL-ND - IC AMP VGA 150MHZ LN LP 16QSOP
AD8330ARQZ-R7-ND - IC AMP VGA 150MHZ LN LP 16QSOP
AD8330ARQZ-ND - IC AMP VGA 150MHZ LN LP 16QSOP
Data Sheet
AD8330
Rev. F | Page 23 of 32
1.2
0
5ns
10ns
15ns
25ns
20ns
1.0
0.8
0.6
0.4
0.2
0
–0.2
0.2
–0.4
–0.6
–0.8
–1.0
–1.2
0
–0.2
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
03217-
063
Figure 62. Typical Pulse Response for Figure 61
The bandwidth from Pin VMAG to these outputs is somewhat
higher than from the normal input pins. Thus, when this pin is
used to rapidly modulate the primary signal, some further
experimentation with response optimization may be required.
In general, the AD8330 is very tolerant of a wide range of
loading conditions.
Preserving Absolute Gain
Although the AD8330 is not laser trimmed, its absolute gain
calibration, based mainly on ratios, is very good. Full details are
found in the Specifications section and in the typical performance
Nevertheless, having finite input and output impedances, the
gain is necessarily dependent on the source and load conditions.
The loss that is incurred when either of these is finite causes an
error in the absolute gain. The absolute gain can also be
uncertain due to the approximately ±20% tolerance in the
absolute value of the input and output impedances.
Often, such losses and uncertainties can be tolerated and
accommodated by a correction to the gain control bias. On the
other hand, the error in the loss can be essentially nulled by
using appropriate modifications to either the source impedance
(RS) or the load impedance (RL), or both (in some cases by
padding them with series or shunt components).
The formulation for this correction technique was previously
described. However, to simplify its use, Table 5 shows spot
values for combinations of RS and RL resulting in an overall loss
that is not dependent on sample-to-sample variations in on chip
resistances. Furthermore, this fixed and predictable loss can be
corrected by an adjustment to VMAG, as indicated in Table 5.
Table 5. Preserving Absolute Gain
Uncorrected Loss
VMAGRequired to
Correct Loss
RS ()
RL ()
Factor
dB
10
15 k
0.980
0.17
0.510
15
10 k
0.971
0.26
0.515
20
7.5 k
0.961
0.34
0.520
30
5.0 k
0.943
0.51
0.530
50
3.0 k
0.907
0.85
0.551
75
2.0 k
0.865
1.26
0.578
100
1.5 k
0.826
1.66
0.605
150
1.0 k
0.756
2.43
0.661
200
750
0.694
3.17
0.720
300
500
0.592
4.56
0.845
500
300
0.444
7.04
1.125
750
200
0.327
9.72
1.531
1 k
150
0.250
12.0
2.000
1.5 k
100
0.160
15.9
3.125
2 k
75
0.111
19.1
4.500
Calculation of Noise Figure
The AD8330 noise is a consequence of its intrinsic voltage noise
spectral density (ENSD) and the current noise spectral density
(INSD). Their combined effect generates a net input noise, VNOISE_IN,
that is a function of the input resistance of the device (RI),
nominally 1 kΩ, and the differential source resistance (RS) as
follows:
(
)
{
}2
2
_
+
=
S
I
NSD
IN
NOISE
R
I
E
V
(16)
Note that purely resistive source and input impedances as a conces-
sion to simplicity is assumed. A more thorough treatment of
noise mechanisms, for the case where the source is reactive, is
beyond the scope of these brief notes. Also note that VNOISE_IN is
the voltage noise spectral density appearing across INHI and
INLO, the differential input pins. In preparing for the calculation
of the noise figure, VSIG is defined as the open-circuit signal
voltage across the source, and VIN is defined as the differential
input to the AD8330. The relationship is simply
(
)
S
I
SIG
IN
R
V
+
=
(17)
At maximum gain, ENSD is 4.1 nV/√Hz, and INSD is 3 pA/√Hz.
Thus, the short-circuit voltage noise is
(
) (
) (
)
{
}=
+
+
=
2
_
0
k
1
Hz
/
pA
3
Hz
/
V
n
1
.
4
IN
NOISE
V
5.08 nV/√Hz
(18)
Next, examine the net noise when RS = RI = 1 kΩ, often incor-
rectly called the matching condition, rather than source impedance
termination, which is the actual situation in this case.
Repeating the procedure,
(
) (
) (
)2
2
_
kΩ
1
kΩ
1
Hz
/
pA
3
Hz
/
nV
1
.
4
+
=
IN
NOISE
V
= 7.3 nV/√Hz
(19)
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