參數(shù)資料
型號(hào)： AD8328ARQZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 18/20頁(yè)
文件大?。?/td> 0K
描述： IC LINE DRIVE CABLE 5V 20-QSOP
產(chǎn)品變化通告： AD8328 Discontinuation 02/Mar/2012
標(biāo)準(zhǔn)包裝： 56
類型： 線路驅(qū)動(dòng)器，發(fā)射器
應(yīng)用： 調(diào)制解調(diào)器，機(jī)頂盒
安裝類型： 表面貼裝
封裝/外殼： 20-SSOP（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 20-QSOP
包裝： 管件
產(chǎn)品目錄頁(yè)面： 765 (CN2011-ZH PDF)
AD8328
Rev. A | Page 7 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
AD8328
TXEN
SDATA
VCC
CLK
VIN+
SLEEP
BYP
NC
VOUT+
NC = NO CONNECT
GND
VIN–
GND
RAMP
VOUT–
GND
VCC
DATEN
GND
03
15
8-
0
05
Figure 5. 20-Lead QSOP Pin Configuration
TOP VIEW
(Not to Scale)
AD8328
1
2
3
4
5
15
14
13
12
11
16
17
20 19 18
67
8
9 10
GND
VIN+
VIN–
GN
D
GN
D
V
CC
V
CC
TX
E
N
GN
D
SL
EEP
DA
T
E
N
S
DAT
A
CL
K
RAMP
VOUT+
VOUT–
BYP
NC
03
15
8-
00
6
Figure 6. 20-Lead LFCSP Pin Configuration
Table 5. 20-Lead QSOP and 20-Lead LFCSP Pin Function Descriptions
Pin No.
20-Lead
QSOP
Pin No.
20-Lead
LFCSP
Mnemonic
Description
1, 3, 4, 7,
11, 20
1, 2, 5, 9,
18, 19
GND
Common External Ground Reference.
2, 19
17, 20
VCC
Common Positive External Supply Voltage. A 0.1 μF capacitor must decouple each pin.
5
3
VIN+
Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.
6
4
VIN
Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 μF capacitor.
8
6
DATEN
Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register.
A Logic 0-to-Logic 1 transition transfers the latched data to the attenuator core (updates the gain)
and simultaneously inhibits serial data transfer into the register.
A Logic 1-to-Logic 0 transition inhibits the data latch (holds the previous gain state) and
simultaneously enables the register for serial data load.
9
7
SDATA
Serial Data Input. This digital input allows an 8-bit serial (gain) word to be loaded into the
internal register with the most significant bit (MSB) first.
10
8
CLK
Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit
master-slave register.
A Logic 0-to-Logic 1 transition latches the data bit, and a Logic 1-to-Logic 0 transfers the data bit
to the slave. This requires the input serial data-word to be valid at or before this clock transition.
12
10
SLEEP
Low Power Sleep Mode. In the sleep mode, the AD8328’s supply current is reduced to 20 μA.
A Logic 0 powers down the part (high ZOUT state), and a Logic 1 powers up the part.
13
11
NC
No Connect.
14
12
BYP
Internal Bypass. This pin must be externally ac-coupled (0.1 μF capacitor).
15
13
VOUT
Negative Output Signal
16
14
VOUT+
Positive Output Signal
17
15
RAMP
External RAMP Capacitor (Optional)
18
16
TXEN
Logic 0 Disables Forward Transmission. Logic 1 enables forward transmission.
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