參數(shù)資料
型號(hào)： AD8305ACP-R2
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 0K
描述： IC LOGARITHM CONV 100DB 16-LFCSP
產(chǎn)品變化通告： Product Discontinuance 27/July/2010
設(shè)計(jì)資源： Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056)
Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector
標(biāo)準(zhǔn)包裝： 1
類型： 對(duì)數(shù)轉(zhuǎn)換器
應(yīng)用： 光纖
安裝類型： 表面貼裝
封裝/外殼： 16-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 16-LFCSP-VQ
包裝： 標(biāo)準(zhǔn)包裝
其它名稱： AD8305ACP-R2DKR
AD8305
Rev. B | Page 16 of 24
USING A NEGATIVE SUPPLY
Most applications of the AD8305 require only a single supply of
3.0 V to 5.5 V. However, to provide further versatility, dual
supplies may be employed, as illustrated in Figure 37.
BIAS
GENERATOR
VLOG
COMM
VNEG
VSUM
IREF
0.5V
80k
0.5V
TEMPERATURE
COMPENSATION
VBE1
VBE2
6.69k
Q1
COMM
20k
451
VREF
VRDZ
14.2k
Q2
INPT
COMM
2.5V
VPOS
BFIN
SCAL
VOUT
ILOG
IPD
RREF
200k
0.5 log10
IPD
1nA
1nF
1k
VBIAS
1nF
1k
12k
5V
CFLT
10nF
8k
–
+
VF
C1
VN
RS ≤
VNEG ≤ –0.5V
–
RS
ISIG = IPD + IREF
Iq + ISIG
VN – VF
Iq + ISIGMAX
0305
3-
036
Figure 37. Negative Supply Application
The use of a negative supply, VN, allows the summing node to
be placed at ground level whenever the input transistor (Q1 in
Figure 33) has a sufficiently negative bias on its emitter. When
VNEG = 0.5 V, the VCE of Q1 and Q2 is the same as for the
default case when VSUM is grounded. This bias does not need
to be accurate, and a poorly defined source can be used. The
source does, however, need to be able to support the quiescent
current as well as the INPT and IREF signal current. For
example, it may be convenient to utilize a forward-biased
junction voltage of about 0.7 V or a Schottky barrier voltage of a
little over 0.5 V. The effect of supply on the dynamic range and
accuracy can be seen in Figure 10.
With the summing node at ground, the AD8305 may now be
used as a voltage-input log amp at either the numerator input,
INPT, or the denominator input, IREF, by inserting a suitably
scaled resistor from the voltage source to the relevant pin. The
overall accuracy for small input voltages is limited by the
voltage offset at the inputs of the JFET op amps.
The use of a negative supply also allows the output to swing
below ground, thereby allowing the intercept to correspond to a
midrange value of IPD. However, the voltage, VLOG, remains
referenced to the ACOM pin, and while it does not swing
negative for default operating conditions, it is free to do so,
thus, adding a resistor from VLOG to the negative supply
lowers all values of VLOG, which raises the intercept. The
disadvantage of this method is that the slope is reduced by the
shunting of the external resistor, and the poorly defined ratio of
on-chip and off-chip resistances causes errors in both the slope
and the intercept.
BIAS
GENERATOR
VLOG
COMM
VNEG
VSUM
IREF
0.5V
80k
0.5V
TEMPERATURE
COMPENSATION
VBE1
6.69k
Q1
COMM
20k
451
VREF
VRDZ
14.2k
Q2
INPT
COMM
2.5V
VPOS
BFIN
SCAL
VOUT
ILOG
5V
0.5 log10
IPD
IREF
+ 2
IPD
IREF
1k
1nF
1k
1nF
28.0k
44.2k
18nF
REFERENCE
DETECTOR
SIGNAL
DETECTOR
PREF
PSIG
33nF
12.1k
–
+
VBE2
03
05
3-
03
7
Figure 38. Optical Absorbance Measurement
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