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參數(shù)資料
| 型號： | AD8304ARU |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 0K |
| 描述： | IC LOGARITHM CONV 160DB 14-TSSOP |
| 設(shè)計資源： | Interfacing ADL5315 to Translinear Logarithmic Amplifier (CN0056) Interfacing ADL5317 High Side Current Mirror to a Translinear Logarithmic Amplifier in an Avalanche Photodiode Power Detector |
| 標準包裝： | 1 |
| 類型： | 對數(shù)轉(zhuǎn)換器 |
| 應(yīng)用： | 光纖 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 14-TSSOP |
| 包裝： | 管件 |
REV. A
AD8304
–17–
Programmable Multidecade Current Source
The AD8304 supports a wide variety of general (nonoptical)
applications. For example, the need frequently arises in test
equipment to provide an accurate current that can be varied over
many decades. This can be achieved using a logarithmic amplifier
as the measuring device in an inverse function loop, as illustrated
in Figure 16. This circuit generates the current:
IpA
SRC
V
SPT
=× ()
100
10
02
/.
(17)
The principle is as follows. The current in QA is forced to supply
a certain IPD by measuring the error between a setpoint VSPT and
VLOG, and nulling this error by integration. This is performed by
the internal op amp and capacitor C1, with a time constant formed
with the internal 5 k
resistor. The choice of C1 in this example
ensures loop stability over the full eight-decade range of output
currents; C2 reduces phase lag. The system is completed with a
10-bit MDAC using VREF as its reference, whose output is scaled
to 1.6 V FS by R1 and R2 (whose parallel sum is also 5 k
).
Transistor QA may be a single bipolar device, which will result in
a small alpha error in ISRC (the current is monitored in the emitter
branch), or a Darlington pair or an MOS device, either of which
ensure a negligible difference between IPD and ISRC. In this example,
the bipolar pair is used. The output voltage compliance is deter-
mined by the collector breakdown voltage of these transistors,
while the minimum voltage depends on where VSUM is placed.
Optional components could be added to put this node and VNEG
at a low enough bias to allow the voltage to go slightly below ground.
Many variations of this basic circuit are possible. For example, the
current can be continuously controlled by a simple voltage, or
by a second current. Larger output currents can be controlled by
setting VSUM to zero and using a current shunt divider.
Characterization Setups and Methods
During the primary characterization of the AD8304, the device
was treated as a high precision current-in logarithmic amplifier
(converter). Rather than attempting to accurately generate photo-
currents by illuminating a photodiode, precision current sources,
like the Keithley 236, were used as input sources. Great care was
taken when applying the low level input currents. The triax output
of the current source was used with the guard connected to VSUM
at the characterization board. On the board the input trace was
guarded by connecting adjacent traces and a portion of an internal
copper layer to the VSUM Pins. One obvious reason for the care
was leakage current. With 0.5 V as the nominal bias on the
INPT Pin, a resistance of 50 G
to ground would cause 10 pA
of leakage, or about one decibel of error at the low end of the
measurement range. Additionally, the high output resistance of
the current source and the long signal cable lengths commonly
needed in characterization make a good receiver for 60 Hz emis-
sions. Good guarding techniques help to reduce the pickup of
unwanted signals.
KEITHLEY 236
INPT
PWDN
VNEG
VPOS
VSUM
VPDB
VREF
VOUT
BFIN
VLOG
AD8304
CHARACTERIZATION
BOARD
TRIAX
CONNECTOR*
*SIGNAL: INPT;
GUARD: VSUM;
SHIELD: GROUND
DC MATRIX, DC SUPPLIES, DMM
RIBBON
CABLE
Figure 18. Primary Characterization Setup
The primary characterization setup shown in Figure 18 is used to
measure the static performance, logarithmic conformance, slope
and intercept, buffer offset and VREF drift with temperature, and
the performance of the VPDB Pin functions. For the dynamic tests,
such as noise and bandwidth, more specialized setups are used.
AD8138
EVALUATION
BOARD
OUTPUT INPUT INPUTA
HP 3577A
NETWORK
ANALYZER
INPUTB
+IN
B
A
VNEG
PWDN
VSUM
INPT
VSUM
VPDB
VREF
ACOM
BFNG
VPS1
VOUT
VPS2
BFIN
VLOG
1
2
3
4
5
6
7
14
13
12
11
10
9
8
POWER
SPLITTER
49.9
0.1 F
+VS
AD8304
Figure 19. Configuration for Buffer Amplifier
Bandwidth Measurement
Figure 19 shows the configuration used to measure the buffer
amplifier bandwidth. The AD8138 Evaluation Board provides a
dc offset at the buffer input, allowing measurement in single-supply
mode. The network analyzer input impedance was set to 1 M
.
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| AD8304ARU-REEL7 | 功能描述:IC LOGARITHMIC CONV 14-TSSOP T/R RoHS:否 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
| AD8304ARUZ | 功能描述:IC LOGARITHM CONV 160DB 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
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| AD8304ARUZ-RL7 | 功能描述:IC LOGARITHM CONV 160DB 14-TSSOP RoHS:是 類別:集成電路 (IC) >> 線性 - 放大器 - 專用 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:60 系列:- 類型:可變增益放大器 應(yīng)用:CATV 安裝類型:表面貼裝 封裝/外殼:20-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:20-TQFN-EP（5x5） 包裝:托盤 |
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