VDD SUPPLY VOLTAGE – Volts LO" />
參數(shù)資料
型號(hào): AD8300ARZ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 5/8頁(yè)
文件大小: 0K
描述: IC DAC 12BIT 3V SRL-IN 8-SOIC
產(chǎn)品培訓(xùn)模塊: Data Converter Fundamentals
DAC Architectures
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 14µs
位數(shù): 12
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
電壓電源: 單電源
功率耗散(最大): 5.1mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 管件
輸出數(shù)目和類型: 1 電壓,單極
采樣率(每秒): 71k
產(chǎn)品目錄頁(yè)面: 785 (CN2011-ZH PDF)
REV. A
AD8300
–5–
2.5
2.0
0
01
6
45
0.5
1.0
1.5
23
VDD SUPPLY VOLTAGE – Volts
LOGIC
THRESHOLD
VOLTAGE
TA = –40 TO +85 C
Figure 5. Logic Input Threshold
Voltage vs. VDD
50
45
0
10
100
1M
10k
100k
40
35
30
25
20
15
10
5
1k
FREQUENCY – Hz
POWER
SUPPLY
REJECTION
dB
VDD = +3V
10%
VDD = +5V
10%
TA = +25 C
DATA = FFFH
Figure 8. Power Supply Rejection
vs. Frequency
CODE 800H TO 7FFH
Figure 11. Midscale Transition
Performance
80
40
–80
02
1
–40
0
60
20
–60
–20
OUTPUT VOLTAGE – Volts
OUTPUT
CURRENT
mA
VDD = +3V
VDD = +5V
VDD = +3V
VDD = +5V
POSITIVE
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
DATA = 800H
RL TIED TO +1.024V
Figure 4. IOUT vs. VOUT
TIME = 100 s/DIV
BROADBAND
NOISE
200
V/DIV
Figure 7. Broadband Noise
3.5
3.0
0
01
5
34
1.5
2.5
2.0
2
LOGIC VOLTAGE – Volts
SUPPLY
CURRENT
mA
VDD = +5V
VDD = +3V
TA = +25 C
DATA = FFFH
1.0
0.5
Figure 10. Supply Current vs. Logic
Input Voltage
HORIZONTAL = 1 s/DIV
Figure 6. Detail Settling Time
HORIZONTAL = 20 s/DIV
Figure 9. Large Signal Settling Time
0.5 s/DIV
Figure 12. Digital Feedthrough vs.
Time
Typical Performance Characteristics–
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