參數(shù)資料
型號(hào): AD826ARZ-REEL7
廠(chǎng)商: Analog Devices Inc
文件頁(yè)數(shù): 3/15頁(yè)
文件大?。?/td> 0K
描述: IC OPAMP VF 50MHZ DUAL LP 8SOIC
標(biāo)準(zhǔn)包裝: 1,000
放大器類(lèi)型: 電壓反饋
電路數(shù): 2
轉(zhuǎn)換速率: 350 V/µs
增益帶寬積: 50MHz
-3db帶寬: 50MHz
電流 - 輸入偏壓: 3.3µA
電壓 - 輸入偏移: 500µV
電流 - 電源: 6.6mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 5 V ~ 36 V,±2.5 V ~ 18 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
AD826
–11–
SINGLE SUPPLY OPERATION
An exciting feature of the AD826 is its ability to perform well in a
single supply configuration (see Figure 37). The AD826 is ideally
suited for applications that require low power dissipation and high
output current and those which need to drive large capacitive
loads, such as high speed buffering and instrumentation.
Referring to Figure 36, careful consideration should be given to
the proper selection of component values. The choices for this
particular circuit are: (R1 + R3) R2 combine with C1 to form a
low frequency corner of approximately 30 Hz.
VS
1/2
AD826
R2
10k
3.3 F
0.01 F
C3
0.1 F
VOUT
R1
9k
R3
1k
C2
0.1 F
VIN
C1
1 F
CL
200pF
RL
150
COUT
Figure 36. Single Supply Amplifier Configuration
R3 and C2 reduce the effect of the power supply changes on the
output by low-pass filtering with a corner at
1
2
πR
3C2
.
The values for RL and CL were chosen to demonstrate the
AD826’s exceptional output drive capability. In this configura-
tion, the output is centered around 2.5 V. In order to eliminate
the static dc current associated with this level, C3 was inserted
in series with RL.
10
90
100
0%
500mV
100ns
500mV
Figure 37. Single Supply Pulse Response, G = +1,
RL = 150
, CL = 200 pF
PARALLEL AMPS PROVIDE 100 mA TO LOAD
By taking advantage of the superior matching characteristics of
the AD826, enhanced performance can easily be achieved by
employing the circuit in Figure 38. Here, two identical cells are
paralleled to obtain even higher load driving capability than that
of a single amplifier (100 mA min guaranteed). R1 and R2 are
included to limit current flow between amplifier outputs that
would arise in the presence of any residual mismatch.
VS
VIN
VOUT
1k
R1
5
R2
5
–VS
1k
RL
1/2
AD826
1/2
AD826
0.1 F
1 F
0.1 F
1 F
Figure 38. Parallel Amp Configuration
REV. C
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