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參數(shù)資料
| 型號： | AD8250-EVALZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION AD8250 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | iCMOS® |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類型： | 儀表 |
| 輸出類型： | 單端 |
| 轉(zhuǎn)換速率： | 25 V/µs |
| -3db帶寬： | 10MHz |
| 電流 - 輸出 / 通道： | 37mA |
| 工作溫度： | -40°C ~ 85°C |
| 電流供應(yīng)（主 IC）： | 4.1mA |
| 電壓 - 電源，單路/雙路(±)： | 10 V ~ 30 V，±5 V ~ 15 V |
| 板類型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD8250 |
| 相關(guān)產(chǎn)品： | AD8250ARMZ-R7DKR-ND - IC AMP INST ICMOS LDRIFT 10MSOP AD8250ARMZ-R7CT-ND - IC AMP INST ICMOS LDRIFT 10MSOP AD8250ARMZ-RL-ND - IC AMP INST ICMOS LDRIFT 10MSOP AD8250ARMZ-R7TR-ND - IC AMP INST ICMOS LDRIFT 10MSOP AD8250ARMZ-ND - IC AMP INST ICMOS LDRIFT 10MSOP |
AD8250
Data Sheet
Rev. C | Page 16 of 24
Table 5. Truth Table Logic Levels for Transparent Gain Mode
WR
A1
A0
Gain
VS
Low
1
VS
Low
High
2
VS
High
Low
5
VS
High
10
Latched Gain Mode
Some applications have multiple programmable devices such as
multiplexers or other programmable gain instrumentation
amplifiers on the same PCB. In such cases, devices can share a
data bus. The gain of the AD8250 can be set using WR as a latch,
allowing other devices to share A0 and A1. Figure 49 shows a
schematic using this method, known as latched gain mode. The
AD8250 is in this mode when WR is held at logic high or logic
low, typically 5 V and 0 V, respectively. The voltages on A0
and A1 are read on the downward edge of the WR signal as it
transitions from logic high to logic low. This latches in the logic
levels on A0 and A1, resulting in a gain change. See the truth
table in Table 6 for more information on these gain changes.
+15V
–15V
A0
A1
WR
+IN
–IN
10μF0.1F
DGND
REF
AD8250
A0
A1
WR
+5V
0V
G = PREVIOUS
STATE
G = 10
06
28
8-
0
56
+
–
NOTE:
1. ON THE DOWNWARD EDGE OF WR, AS IT TRANSITIONS
FROM LOGIC HIGH TO LOGIC LOW, THE VOLTAGES ON A0
AND A1 ARE READ AND LATCHED IN, RESULTING IN A
GAIN CHANGE. IN THIS EXAMPLE, THE GAIN SWITCHES TO G = 10.
Figure 49. Latched Gain Mode, G = 10
Table 6. Truth Table Logic Levels for Latched Gain Mode
WR
A1
A0
Gain
High to low
Low
Change to 1
High to low
Low
High
Change to 2
High to low
High
Low
Change to 5
High to low
High
Change to 10
Low to low
X1
No change
Low to high
X1
No change
High to high
X1
No change
1 X = don’t care.
On power-up, the AD8250 defaults to a gain of 1 when in latched
gain mode. In contrast, if the AD8250 is configured in transparent
gain mode, it starts at the gain indicated by the voltage levels on
A0 and A1 at power-up.
Timing for Latched Gain Mode
In latched gain mode, logic levels at A0 and A1 have to be held
for a minimum setup time, tSU, before the downward edge of
WR latches in the gain. Similarly, they must be held for a
minimum hold time of tHD after the downward edge of WR to
ensure that the gain is latched in correctly. After tHD, A0 and A1
can change logic levels, but the gain does not change (until the
next downward edge of WR). The minimum duration that WR
can be held high is t WR-HIGH, and the minimum duration that
WR can be held low is t WR-LOW. Digital timing specifications are
listed in Table 2. The time required for a gain change is dominated
by the settling time of the amplifier. A timing diagram is shown
When sharing a data bus with other devices, logic levels applied
to those devices can potentially feed through to the output of
the AD8250. Feedthrough can be minimized by decreasing the
edge rate of the logic signals. Furthermore, careful layout of the
PCB also reduces coupling between the digital and analog portions
of the board. Pull-up or pull-down resistors should be used to
provide a well-defined voltage at the A0 and A1 pins.
A0, A1
WR
tSU
tHD
tWR-HIGH
tWR-LOW
0
62
88-
0
57
Figure 50. Timing Diagram for Latched Gain Mode
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