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| 型號(hào)： | AD8230YRZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 0K |
| 描述： | IC AMP CHOPPER R-R PREC 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 2 V/µs |
| 電流 - 輸入偏壓： | 150pA |
| 電壓 - 輸入偏移： | 20µV |
| 電流 - 電源： | 3.2mA |
| 電流 - 輸出 / 通道： | 15mA |
| 電壓 - 電源，單路/雙路(±)： | 8 V ~ 16 V，±4 V ~ 8 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 771 (CN2011-ZH PDF) |
AD8230
Rev. B | Page 13 of 16
INPUT VOLTAGE RANGE
The input common-mode range of the AD8230 is rail to rail.
However, the differential input voltage range is limited to
approximately 750 mV. The AD8230 does not phase invert
when its inputs are overdriven.
INPUT PROTECTION
The input voltage is limited to within 0.6 V beyond the supply
rails by the internal ESD protection diodes. Resistors and low
leakage diodes can be used to limit excessive, external voltage
and current from damaging the inputs, as shown in Figure 37.
Figure 39 shows an overvoltage protection circuit between the
thermocouple and the AD8230.
2
6
1
7
5
8
4
3
AD8230
VOUT
–VS
+VS
0.1F
200
19.1k
BAV199
–VS
+VS
2.49k
BAV199
–VS
+VS
0.1F
0
506
3-
0
37
Figure 37. Overvoltage Input Protection
POWER SUPPLY BYPASSING
A regulated dc voltage should be used to power the
instrumentation amplifier. Noise on the supply pins can
adversely affect performance. Bypass capacitors should be
used to decouple the amplifier.
The AD8230 has internal clocked circuitry that requires
adequate supply bypassing. A 0.1 μF capacitor should be placed
as close to each supply pin as possible. As shown in Figure 32, a
10 μF tantalum capacitor can be used further away from the part.
POWER SUPPLY BYPASSING FOR MULTIPLE
CHANNEL SYSTEMS
The best way to prevent clock interference in multichannel
systems is to lay out the PCB with a star node for the positive
supply and a star node for the negative supply. Using such a
technique, crosstalk between clocks is minimized. If laying out
star nodes is not feasible, use wide traces to minimize parasitic
inductance and decouple frequently along the power supply
traces. Examples are shown in Figure 38. Care and forethought
go a long way in maximizing performance.
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
10F
–VS
+VS
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
8
7
6
5
1
2
3
4
–VS
+VS
AD8230
0.1F
10F
STAR +VS
STAR –VS
05
06
3-
0
38
Figure 38. Use Star Nodes for +VS and VS or Use Thick Traces and Decouple Frequently Along the Supply Lines
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