T = 25掳C, VS = 卤15 V, " />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� AD8228BRMZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋佹暩(sh霉)锛� 24/24闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC AMP INST PREC LDRIFT LN 8MSOP
妯欐簴鍖呰锛� 50
鏀惧ぇ鍣ㄩ鍨嬶細 鍎€琛�
闆昏矾鏁�(sh霉)锛� 1
杞�(zhu菐n)鎻涢€熺巼锛� 2.5 V/µs
-3db甯跺锛� 650kHz
闆绘祦 - 杓稿叆鍋忓锛� 400pA
闆诲 - 杓稿叆鍋忕Щ锛� 50µV
闆绘祦 - 闆绘簮锛� 850µA
闆绘祦 - 杓稿嚭 / 閫氶亾锛� 18mA
闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� 4.6 V ~ 36 V锛�±2.3 V ~ 18 V
宸ヤ綔婧害锛� -40°C ~ 85°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-MSOP
鍖呰锛� 绠′欢
AD8228
Rev. 0 | Page 9 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
T = 25掳C, VS = 卤15 V, RL = 10 k惟, unless otherwise noted.
70
60
50
40
30
20
10
0
鈥�100
鈥�50
0
50
100
G10 SYSTEM VOS RTI @ 15V (V)
HI
T
S
07
03
5-
0
43
MEAN: 鈥�5.5
SD: 12.4
Figure 3. Typical Distribution of Input Offset Voltage (G = 10)
60
50
40
30
20
10
0
鈥�1.5
鈥�1.0
鈥�0.5
0
0.5
1.0
1.5
G10 SYSTEM VOS DRIFT RTI (V)
HI
T
S
07
03
5-
0
45
MEAN: 鈥�0.079
SD: 0.27
Figure 4. Typical Distribution of Input Offset Voltage Drift (G = 10)
80
60
40
20
0
鈥�100
鈥�50
0
50
100
G100 SYSTEM VOS RTI @ 15V (V)
HI
T
S
07
03
5-
0
46
MEAN: 7.1
SD: 10.1
Figure 5. Typical Distribution of Input Offset Voltage (G = 100)
100
80
60
40
20
0
鈥�1.0
鈥�0.5
0
0.5
1.0
1.5
G100 SYSTEM VOS DRIFT RTI (V)
HI
T
S
07
03
5-
0
47
MEAN: 0.20
SD: 0.12
Figure 6. Typical Distribution of Input Offset Voltage Drift (G = 100)
100
80
60
40
20
0
鈥�3
鈥�2
鈥�1
0
1
2
3
CMRR G100 RTI (V/V)
HI
T
S
07
03
5-
0
48
MEAN: 0.29
SD: 0.27
Figure 7. Typical Distribution for CMR (G = 100)
100
120
80
60
40
20
0
1.5
鈥�0.5
0
0.5
1.0
NEG IBIAS CURRENTS 卤15V (nA)
HI
T
S
07
03
5-
0
49
MEAN: 0.42
SD: 0.08
Figure 8. Typical Distribution of Input Bias Current
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