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    參數(shù)資料
    型號(hào): AD8205WYRZ
    廠商: Analog Devices Inc
    文件頁數(shù): 11/12頁
    文件大小: 0K
    描述: IC AMP DIFF 42V SGL 8SOIC
    標(biāo)準(zhǔn)包裝: 98
    放大器類型: 差分
    電路數(shù): 1
    轉(zhuǎn)換速率: 0.5 V/µs
    -3db帶寬: 50kHz
    電壓 - 輸入偏移: 2000µV
    電流 - 電源: 2mA
    電壓 - 電源,單路/雙路(±): 4.5 V ~ 5.5 V
    工作溫度: -40°C ~ 125°C
    安裝類型: 表面貼裝
    封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
    供應(yīng)商設(shè)備封裝: 8-SO
    包裝: 管件
    AD8205
    Data Sheet
    Rev. | Page 8 of 12
    THEORY OF OPERATION
    The AD8205 is a single-supply difference amplifier that uses a
    unique architecture to accurately amplify small differential
    current shunt voltages in the presence of rapidly changing
    common-mode voltages.
    In typical applications, the AD8205 is used to measure current
    by amplifying the voltage across a current shunt placed across
    the inputs.
    The gain of the AD8205 is 50 V/V, with an accuracy of 1.2%.
    This accuracy for the Y and W Grade is guaranteed over the
    operating temperature range of 40°C to +125°C. The H Grade
    version of the AD8205 is specified for operation from 40°C to
    +150°C.
    The input offset is less than 2 mV referred to the input at 25°C,
    and 4.5 mV maximum referred to the input over the full
    operating temperature range for the packaged part.
    The AD8205 operates with a single supply from 4.5 V to
    10 V (absolute maximum = 12.5 V). The supply current is
    less than 2 mA.
    High accuracy trimming of the internal resistors allows the
    AD8205 to have a common-mode rejection ratio better than
    78 dB from dc to 20 kHz.
    The output offset can be adjusted from 0.05 V to 4.8 V (V+ = 5 V)
    for unipolar and bipolar operation.
    The AD8205 consists of two amplifiers (A1 and A2), a resistor
    network, small voltage reference, and a bias circuit (not shown),
    The set of input attenuators preceding A1 consist of RA, RB, and
    RC, which reduce the common-mode voltage to match the input
    voltage range of A1. The two attenuators form a balanced bridge
    network. When the bridge is balanced, the differential voltage
    created by a common-mode voltage is 0 V at the inputs of A1.
    The input attenuation ratio is 1/16.7. The combined series
    resistance of RA, RB, and RC is approximately 200 k ± 20%.
    By attenuating the voltages at Pin 1 and Pin 8, the A1 amplifier
    inputs are held within the power supply range, even if Pin 1 and
    Pin 8 exceed the supply or fall below common (ground). A
    reference voltage of 250 mV biases the attenuator above ground.
    This allows the amplifier to operate in the presence of negative
    common-mode voltages.
    The input network also attenuates normal (differential) mode
    voltages. A1 amplifies the attenuated signal by 26. The input
    and output of this amplifier are differential to maximize the ac
    common-mode rejection.
    A2 converts the differential voltage from A1 into a single-ended
    signal and provides further amplification. The gain of this
    second stage is 32.15.
    The reference inputs, VREF1 and VREF2, are tied through resistors
    to the positive input of A2, which allows the output offset to be
    adjusted anywhere in the output operating range. The gain is
    1 V/V from the reference pins to the output when the reference
    pins are used in parallel. The gain is 0.5 V/V when they are used
    to divide the supply.
    The ratios of Resistors RA, RB, RC, RD, and RF are trimmed to a
    high level of precision to allow the common-mode rejection
    ratio to exceed 80 dB. This is accomplished by laser trimming
    the resistor ratio matching to better than 0.01%.
    The total gain of 50 is made up of the input attenuation of
    1/16.7 multiplied by the first stage gain of 26 and the second
    stage gain of 32.15.
    The output stage is Class A with a PNP pull-up transistor and a
    300 A current sink pull-down.
    04315-0-012
    AD8205
    +IN
    –IN
    250mV
    GND
    A1
    A2
    RA
    RB
    RF
    RD
    RE
    RF
    RC
    VOUT
    RREF
    VREF1
    VREF2
    Figure 13. Simplified Schematic
    D
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