參數(shù)資料
型號(hào)： AD8197BASTZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/28頁(yè)
文件大小： 0K
描述： IC SWITCH DVI/HDMI 4:1 100-LQFP
標(biāo)準(zhǔn)包裝： 1,000
功能： 開(kāi)關(guān)
電路： 1 x 16:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-LQFP（14x14）
包裝： 帶卷 (TR)
AD8197B
Rev. 0 | Page 26 of 28
the AD8197B and do not need to be routed with the same strict
considerations as the high speed TMDS signals.
In general, it is sufficient to route each auxiliary signal as a
single-ended trace. These signals are not sensitive to impedance
discontinuities, do not require a reference plane, and can be
routed on multiple layers of the PCB. However, it is best to
follow strict layout practices whenever possible to prevent the
PCB design from affecting the overall application. The specific
routing of the HPD, CEC, and DDC lines depends upon the
application in which the AD8197B is being used.
For example, the maximum speed of signals present on the
auxiliary lines is 100 kHz I2C data on the DDC lines; therefore,
any layout that enables 100 kHz I2C to be passed over the DDC
bus should suffice. The HDMI 1.3 specification, however, places
a strict 50 pF limit on the amount of capacitance that can be
measured on either SDA or SCL at the HDMI input connector.
This 50 pF limit includes the HDMI connector, the PCB, and
whatever capacitance is seen at the input of the AD8197B, or an
equivalent receiver. There is a similar limit of 100 pF of input
capacitance for the CEC line.
The parasitic capacitance of traces on a PCB increases with
trace length. To help ensure that a design satisfies the HDMI
specification, the length of the CEC and DDC lines on the PCB
should be made as short as possible. Additionally, if there is a
reference plane in the layer adjacent to the auxiliary traces in
the PCB stack-up, relieving or clearing out this reference plane
immediately under the auxiliary traces significantly decreases
the amount of parasitic trace capacitance. An example of the
board stackup is shown in Figure 33.
PCB DIELECTRIC
LAYER 1: SIGNAL (MICROSTRIP)
SILKSCREEN
PCB DIELECTRIC
LAYER 2: GND (REFERENCE PLANE)
LAYER 3: PWR (REFERENCE PLANE)
LAYER 4: SIGNAL (MICROSTRIP)
W
3W
REFERENCE LAYER
RELIEVED UNDERNEATH
MICROSTRIP
07
01
5-
03
2
Figure 33. Example Board Stackup
HPD is a dc signal presented by a sink to a source to indicate
that the source EDID is available for reading. The placement
of this signal is not critical, but it should be routed as directly
as possible.
When the AD8197B is powered up, one set of the auxiliary inputs
is passively routed to the outputs. In this state, the AD8197B
looks like a 100 Ω resistor between the selected auxiliary inputs
and the corresponding outputs as illustrated in Figure 27. The
AD8197B does not buffer the auxiliary signals; therefore, the
input traces, output traces, and the connection through the
AD8197B all must be considered when designing a PCB to meet
HDMI/DVI specifications. The unselected auxiliary inputs of
the AD8197B are placed into a high impedance mode when the
device is powered up. To ensure that all of the auxiliary inputs
of the AD8197B are in a high impedance mode when the device
is powered off, it is necessary to power the AMUXVCC supply
as illustrated in Figure 28.
In contrast to the auxiliary signals, the AD8197B buffers the
TMDS signals, allowing a PCB designer to layout the TMDS
inputs independently of the outputs.
Power Supplies
The AD8197B has five separate power supplies referenced to
two separate grounds. The supply/ground pairs are:
AVCC/AVEE
VTTI/AVEE
VTTO/AVEE
DVCC/DVEE
AMUXVCC/DVEE
The AVCC/AVEE (3.3 V) and DVCC/DVEE (3.3 V) supplies
power the core of the AD8197B. The VTTI/AVEE supply (3.3 V)
powers the input termination (see Figure 25). Similarly, the
VTTO/AVEE supply (3.3 V) powers the output termination
(see Figure 26). The AMUXVCC/DVEE supply (3.3 V to 5 V)
powers the auxiliary multiplexer core and determines the maxi-
mum allowed voltage on the auxiliary lines. For example, if the
DDC bus is using 5 V I2C, then AMUXVCC should be connected
to +5 V relative to DVEE.
In a typical application, all pins labeled AVEE or DVEE
should be connected directly to ground. All pins labeled AVCC,
DVCC, VTTI, or VTTO should be connected to 3.3 V, and
Pin AMUXVCC should be tied to 5 V. The supplies can also be
powered individually, but care must be taken to ensure that
each stage of the AD8197B is powered correctly.
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