參數(shù)資料
型號(hào): AD8197ASTZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 22/32頁
文件大?。?/td> 0K
描述: IC SWITCH DVI/HDMI 4:1 100-LQFP
標(biāo)準(zhǔn)包裝: 1,000
功能: 開關(guān)
電路: 1 x 16:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(14x14)
包裝: 帶卷 (TR)
AD8197
Rev. 0 | Page 29 of 32
Power Supply Bypassing
The AD8197 requires minimal supply bypassing. When
powering the supplies individually, place a 0.01 μF capacitor
between each 3.3 V supply pin (AVCC, DVCC, VTTI, and VTTO)
and ground to filter out supply noise. Generally, bypass capacitors
should be placed near the power pins and should connect directly
to the relevant supplies (without long intervening traces). For
example, to improve the parasitic inductance of the power supply
decoupling capacitors, minimize the trace length between
capacitor landing pads and the vias as shown in Figure 34.
EXTRA ADDED INDUCTANCE
RECOMMENDED
NOT RECOMMENDED
06
471-
033
Figure 34. Recommended Pad Outline for Bypass Capacitors
In applications where the AD8197 is powered by a single 3.3 V
supply, it is recommended to use two reference supply planes
and bypass the 3.3 V reference plane to the ground reference
plane with one 220 pF, one 1000 pF, two 0.01 μF, and one 4.7 μF
capacitors. The capacitors should via down directly to the
supply planes and be placed within a few centimeters of the
AD8197. The AMUXVCC supply does not require additional
bypassing. This bypassing scheme is illustrated in Figure 35.
AD8197
06
47
1-
03
4
Figure 35. Example Placement of Power Supply Decoupling Capacitors
Around the AD8197
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