參數(shù)資料
型號(hào): AD8190ACPZ
廠商: Analog Devices Inc
文件頁數(shù): 21/24頁
文件大?。?/td> 0K
描述: IC SW HDMI/DVI 2:1 EQUAL 56LFCSP
標(biāo)準(zhǔn)包裝: 1
類型: HDMI/DVI 開關(guān)
應(yīng)用: DVI,HDMI 信號(hào)開關(guān)
安裝類型: 表面貼裝
封裝/外殼: 56-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 56-LFCSP-VQ(8x8)
包裝: 托盤
AD8190
Rev. 0 | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
AVCC
2
IN_A0
3
IP_A0
4
AVEE
5
IN_A1
6
IP_A1
7
VTTI
8
IN_A2
9
IP_A2
10
AVCC
11
IN_A3
12
IP_A3
13
AVEE
14
I2C_ADDR
35
IP_B1
36
VTTI
37
IN_B2
38
IP_B2
39
AVEE
40
IN_B3
41
IP_B3
42
AVCC
34
IN_B1
33
AVCC
32
IP_B0
31
IN_B0
30
AVEE
29
I2C_SDA
15
D
V
C
16
O
N
0
17
O
P
0
19
O
N
1
21
D
V
C
20
O
P
1
22
O
N
2
23
O
P
2
24
V
T
O
25
O
N
3
26
O
P
3
27
R
E
S
E
T
28
I2
C
_
S
C
L
18
V
T
O
45
A
U
X
_
B
1
46
A
U
X
_
B
0
47
A
M
U
X
V
C
48
A
U
X
_
C
O
M
3
49
A
U
X
_
C
O
M
2
50
A
U
X
_
C
O
M
1
51
A
U
X
_
C
O
M
0
52
D
V
E
53
A
U
X
_
A
3
54
A
U
X
_
A
2
44
A
U
X
_B
2
43
A
U
X
_
B
3
TOP VIEW
(Not to Scale)
AD8190
55
A
U
X
_
A
1
56
A
U
X
_
A
0
NOTES
1. THE AD8190 LFCSP HAS AN EXPOSED PADDLE (ePAD) ON THE UNDERSIDE
OF THE PACKAGE WHICH AIDS IN HEAT DISSIPATION. THE ePAD MUST BE
ELECTRICALLY CONNECTED TO THE AVEE SUPPLY PLANE IN ORDER TO
MEET THERMAL SPECIFICATIONS.
06
12
2-
00
3
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1, 10, 33, 42
AVCC
Power
Positive Analog Supply. 3.3 V nominal.
2
IN_A0
HS I
High Speed Input Complement.
3
IP_A0
HS I
High Speed Input.
4, 13, 30, 39, ePAD
AVEE
Power
Negative Analog Supply. 0 V nominal.
5
IN_A1
HS I
High Speed Input Complement.
6
IP_A1
HS I
High Speed Input.
7, 36
VTTI
Power
Input Termination Supply. Nominally connected to AVCC.
8
IN_A2
HS I
High Speed Input Complement.
9
IP_A2
HS I
High Speed Input.
11
IN_A3
HS I
High Speed Input Complement.
12
IP_A3
HS I
High Speed Input.
14
I2C_ADDR
Control
I2C Address LSB.
15, 21
DVCC
Power
Positive Digital Power Supply. 3.3 V nominal.
16
ON0
HS O
High Speed Output Complement.
17
OP0
HS O
High Speed Output.
18, 24
VTTO
Power
Output Termination Supply. Nominally connected to AVCC.
19
ON1
HS O
High Speed Output Complement.
20
OP1
HS O
High Speed Output.
22
ON2
HS O
High Speed Output Complement.
23
OP2
HS O
High Speed Output.
25
ON3
HS O
High Speed Output Complement.
26
OP3
HS O
High Speed Output.
27
AA
RESETEE
EA
Control
Configuration Registers Reset. This pin is normally pulled up to DVCC.
28
I2C_SCL
Control
I2C Clock.
29
I2C_SDA
Control
I2C Data.
31
IN_B0
HS I
High Speed Input Complement.
32
IP_B0
HS I
High Speed Input.
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