VREF 5V 10k 1F CAP MUST BE LARGE ENOUGH TO ABSORB TRANSIENT CURREN" />
參數(shù)資料
型號(hào)： AD8189ARUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 0K
描述： IC MULTIPLEXER TRPL 2X1 24TSSOP
標(biāo)準(zhǔn)包裝： 62
功能： 多路復(fù)用器
電路： 3 x 2:1
電壓電源： 單電源
電壓 - 電源，單路/雙路(±)： 3.5 V ~ 5.5 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 管件
AD8188/AD8189
Rev. 0 | Page 16 of 24
VREF
5V
10k
1F
CAP MUST BE LARGE
ENOUGH TO ABSORB
TRANSIENT CURRENTS
WITH MINIMUM BOUNCE.
062
39
-049
Figure 49. Alternate Method for Synthesis of a False Ground Reference
AC-COUPLED INPUTS
Using ac-coupled inputs presents an interesting challenge for
video systems operating from a single 5 V supply. In NTSC and
PAL video systems, 700 mV is the approximate difference
between the maximum signal voltage and black level. It is
assumed that sync has been stripped. However, given the two
pathological cases shown in Figure 50, a dynamic range of twice
the maximum signal swing is required if the inputs are to be
ac-coupled. A possible solution is to use a dc restore circuit
before the mux.
+700mV
–700mV
+5V
GND
VAVG
VSIGNAL
VREF
WHITE LINE WITH BLACK PIXEL
BLACK LINE WITH WHITE PIXEL
VINPUT = VREF + VSIGNAL
VREF ~ VAVG
VREF IS A DC VOLTAGE
SET BY THE RESISTORS
06
23
9-
05
0
Figure 50. Pathological Case for Input Dynamic Range
TOLERANCE TO CAPACITIVE LOAD
Op amps are sensitive to reactive loads. A capacitive load at the
output appears in parallel with an effective resistance (REFF) of
REFF
= (RL || rO)
where RL is the discrete resistive load, and rO is the open loop
output impedance, approximately 15 Ω for these muxes.
The load pole (fLOAD) at
L
EFF
LOAD
C
R
f
π
=
2
1
can seriously degrade phase margin and, therefore, stability. The
old workaround is to place a small series resistor directly at the
output to isolate the load pole. While effective, this ruse also
affects the dc and termination characteristics of a 75 Ω system.
The AD8188 and AD8189 are built with a variable compensation
scheme that senses the output reactance and trades bandwidth
for phase margin, ensuring faster settling and lower overshoot
at higher capacitive loads.
SECONDARY SUPPLIES AND SUPPLY BYPASSING
The high current output transistors are given their own supply
pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise
on-chip and to improve output isolation. Because these
secondary, high current supply pins are not connected on-chip
to the primary analog supplies, VCC/VEE (Pin 6, Pin 7, Pin 9,
Pin 11, Pin 13, and Pin 24), some care should be taken to ensure
that the supply bypass capacitors are connected to the correct
pins. At a minimum, the primary supplies should be bypassed.
Pin 6 and Pin 7 can be a convenient place to accomplish this.
Stacked power and ground planes are a convenient way to
bypass the high current supply pins (see Figure 51).
MUX1
MUX2
MUX3
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
0.1F
1F
VCC
DVCC
VEE
OUT2
VCC
OUT1
VEE
OUT0
VCC
OE
IN0A
IN0B
VEE
IN1B
VEE
IN2B
VEE
VCC
IN2A
VREF
IN1A
DGND
SEL A/B
06
23
9-
05
1
Figure 51. Detail of Primary and Secondary Supplies
SPLIT-SUPPLY OPERATION
Operating from split supplies (for example, [+3 V/2 V] or
±2.5 V) simplifies the selection of the VREF voltage and load
resistor termination voltage. In this case, it is convenient to tie
VREF to ground. The logic inputs are internally level-shifted to
allow the digital supplies and logic inputs to operate from 0 V
and 5 V when powering the analog circuits from split supplies.
The maximum voltage difference between DVCC and VEE must
not exceed 8 V (see Figure 52).
8V MAX
(+5V)
(0V)
(+2.5V)
(–2.5V)
DVCC
DGND
VCC
VEE
DIGITAL SUPPLIES
ANALOG SUPPLIES
06
23
9-
05
2
Figure 52. Split-Supply Operation
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