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參數(shù)資料
| 型號： | AD8141ACPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO AMP TRPL DIFF 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 應(yīng)用： | 驅(qū)動器 |
| 輸出類型： | 差分 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 275MHz |
| 轉(zhuǎn)換速率： | 1150 V/µs |
| 電流 - 電源： | 44mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.25 V ~ 2.75 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-WFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-WQ（4x4） |
| 包裝： | 帶卷 (TR) |
Data Sheet
AD8141/AD8142
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Supply Voltage
5.5 V
HSYNC, VSYNC, SYNC LEVEL
VS/VS+
Power Dissipation
Input Common-Mode Voltage
VS/VS+
Storage Temperature Range
65°C to +125°C
Operating Temperature Range
40°C to +85°C
Lead Temperature (Soldering 10 sec)
300°C
Junction Temperature
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
Table 3. Thermal Resistance with the Underside Pad
Thermally Connected to a Copper Plane
Package Type/PCB Type
θJA
θJC
Unit
24-Lead LFCSP/4-Layer
38
4.7
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation in the AD8141/AD8142
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
a junction temperature of 175°C for an extended period can result
in changes in the silicon devices potentially causing failure.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of differential and
common-mode currents flowing to the loads, as well as currents
flowing through the internal differential and common-mode
feedback loops. The internal resistor tap used in the common-
mode feedback loop places a 12.5 k differential load on the
output. RMS output voltages should be considered when
dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces, through holes, ground,
and power planes reduce the θJA. The exposed pad on the underside
of the package must be soldered to a pad on the PCB surface that is
thermally connected to a PCB plane to achieve the specified θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 24-lead LFCSP
(38°C/W) on a JEDEC standard 4-layer board with the underside
paddle soldered to a pad that is thermally connected to a PCB
plane. θJA values are approximations.
0
1
2
3
4
5
6
–40
–20
0
20
40
60
80
MA
XI
MU
M
PO
W
ER
D
ISSI
PA
TION
(
W)
AMBIENT TEMPERATURE (°C)
09461-
055
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
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