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參數(shù)資料
| 型號： | AD8133ACPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 13/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP DIFF TRPL LDIST 24LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 3 |
| 輸出類型： | 差分 |
| 轉(zhuǎn)換速率： | 1600 V/µs |
| -3db帶寬： | 450MHz |
| 電流 - 輸入偏壓： | 67µA |
| 電壓 - 輸入偏移： | 6000µV |
| 電流 - 電源： | 28mA |
| 電流 - 輸出 / 通道： | 90mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 12 V，±2.25 V ~ 6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 765 (CN2011-ZH PDF) |
| 其它名稱： | AD8133ACPZ-REEL7DKR |
AD8133
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8133
OPD
1
VS– 2
–IN A
3
+IN A
4
VS– 5
VOCMC
VS+
–IN C
+IN C
VS–
18
17
16
15
14
–OUT A
6
–OUT C
13
V
S+
–I
N
B
+IN
B
V
S–
V
OCM
A
24
23
22
21
20
V
OCM
B
19
+OU
T
A
V
S+
+OU
T
B
–OU
T
B
V
S+
7
8
9
10
11
+OU
T
C
12
04769-0-001
A
B
C
Figure 4. 24-Lead LFCSP
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
OPD
Output Pull-Down
2, 5, 14, 21
VS
Negative Power Supply Voltage
3
IN A
Inverting Input, Amplifier A
4
+IN A
Noninverting Input, Amplifier A
6
OUT A
Negative Output, Amplifier A
7
+OUT A
Positive Output, Amplifier A
8, 11, 17, 24
VS+
Positive Power Supply Voltage
9
+OUT B
Positive Output, Amplifier B
10
OUT B
Negative Output, Amplifier B
12
+OUT C
Positive Output, Amplifier C
13
OUT C
Negative Output, Amplifier C
15
+IN C
Noninverting Input, Amplifier C
16
IN C
Inverting Input, Amplifier C
18
VOCMC
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier C
19
VOCMB
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier B
20
VOCMA
Voltage Applied to This Pin Controls Output Common-Mode Voltage, Amplifier A
22
+IN B
Noninverting Input, Amplifier B
23
IN B
Inverting Input, Amplifier B
AD8133
+
–
53.6
53.6
RL, dm 200 VOUT, dm
+
–
VOCM
1.5k
1.5k
VTEST
TEST
SIGNAL
SOURCE
50
50
750
750
MIDSUPPLY
0.1
F ON ALL V
S+ PINS
0.1
F ON ALL V
S– PINS
VS–
VS+
04769-0-035
+5V
–5V
Figure 5. Basic Test Circuit
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