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| 型號： | AD8129ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 30/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP DIFF LN LDIST 40MA 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 放大器類型： | 差分 |
| 電路數(shù)： | 1 |
| 轉(zhuǎn)換速率： | 1070 V/µs |
| -3db帶寬： | 200MHz |
| 電流 - 輸入偏壓： | 500nA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 13mA |
| 電流 - 輸出 / 通道： | 40mA |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 25.2 V，±2.25 V ~ 12.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 帶卷 (TR) |
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AD8129/AD8130
Rev. C | Page 35 of 40
One way to accomplish this is to drive both REF and RG with
the desired offset signal (see Figure 139). Superposition can be
used to solve this circuit. First, break the connection between
VOFFSET and RG. With RG grounded, the gain from Pin 4 to VOUT
is 1 + RF/RG. With Pin 4 grounded, the gain though RG to VOUT
is RF/RG. The sum of these is 1. If VREF is delivered from a low
impedance source, this works fine. However, if the delivered
offset voltage is derived from a high impedance source, such as
a voltage divider, its impedance affects the gain equation. This
makes the circuit more complicated because it creates an
interaction between the gain and offset voltage.
VOUT =
VIN × (1 + RF/RG)+VOFFSET
–V
+V
VIN
VOFFSET
–VS
PD
+VS
+
RF
RG
AD8129/
AD8130
6
2
5
4
8
1
37
0.1
μF
10
μF
0.1
μF
10
μF
02464-140
Figure 139. In this Circuit, VOFFSET Appears at the Output with Unity Gain. This
Circuit Works Well if the VOFFSET Source Impedance Is Low.
A way around this is to apply the offset voltage to a voltage
divider whose attenuation factor matches the gain of the
amplifier and then apply this voltage to the high impedance
REF input. This circuit first divides the desired offset voltage
by the gain, and the amplifier multiplies it back up to unity (see
VOUT =
VIN × (1 + RF/RG)+VOFFSET
–V
+V
VIN
–VS
PD
+VS
+
RF
RG
VOFFSET
RF
AD8129/
AD8130
6
2
5
4
8
1
37
0.1
μF
10
μF
0.1
μF
10
μF
02464-141
Figure 140. Adding an Attenuator at the Offset Input Causes It to Appear at
the Output with Unity Gain.
RESISTORLESS GAIN OF 2
The voltage applied to the REF input (Pin 4) can also be a high
bandwidth signal. If a unity-gain AD8130 has both +IN and
REF driven with the same signal, there is unity gain from VIN
and unity gain from VREF. Thus, the circuit has a gain of 2 and
requires no resistors (see Figure 141).
VOUT
–V
+V
VIN
–VS
PD
+VS
+
AD8130
6
2
5
4
8
1
37
0.1
μF
10
μF
0.1
μF10μF
02464-142
Figure 141. Gain-of-2 Connections with No Resistors
SUMMER
A general summing circuit can be made by the previous
technique. A unity-gain configured AD8130 has one signal
applied to +IN, while the other signal is applied to REF. The
output is the sum of the two input signals (see Figure 142).
VOUT = V1 + V2
V1
V2
–V
+V
–VS
+VS
+
AD8130
6
2
5
4
8
1
37
0.1
μF
10
μF
0.1
μF10μF
02464-143
PD
Figure 142. A Summing Circuit that is Noninverting
with High Input Impedance
This circuit offers several advantages over a conventional op
amp inverting summing circuit. First, the inputs are both high
impedance and the circuit is noninverting. It would require
significant additional circuitry to make an op amp summing
circuit that has high input impedance and is noninverting.
Another advantage is that the AD8130 circuit still preserves the
full bandwidth of the part. In a conventional summing circuit,
the noise gain is increased for each additional input, so the
bandwidth response decreases accordingly. By this technique,
four signals can be summed by applying them to two AD8130s
and then summing the two outputs by a third AD8130.
CABLE-TAP AMPLIFIER
It is often desirable to have a video signal drive several pieces of
equipment. However, the cable should only be terminated once at
its endpoint; therefore, it is not appropriate to have a termination
at each device. A loop-through connection allows a device to tap
the video signal while not disturbing it by any excessive loading.
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