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參數(shù)資料
| 型號： | AD8123ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC RCVR TRPL DIFF EQUAL 40LFCSP |
| 標準包裝： | 1 |
| 類型： | 接收器 |
| 驅動器/接收器數(shù)： | 0/3 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 托盤 |
AD8123
Rev. A | Page 12 of 16
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8123 is useful in many systems that transport computer
video signals, which are typically comprised of red, green, and
blue (RGB) video signals and separate horizontal and vertical
sync signals. Because the sync signals are separate and not
embedded in the color signals, it is advantageous to transmit
them using a simple scheme that encodes them among the three
common-mode voltages of the RGB signals. The AD8134,
complements to the AD8123 because they perform the sync
pulse encoding with the necessary circuitry on-chip.
The sync encoding equations follow:
[ H
V
K
V
Red
CM
=
2
]
(1)
[
]
(2)
V
2
= K
V
Green
CM
[ H
V
K
V
Blue
CM
+
=
2
]
(3)
where:
Red VCM, Green VCM, and Blue VCM are the transmitted common-
mode voltages of the respective color signals.
K is an adjustable gain constant that is set by the driver.
V and H are the vertical and horizontal sync pulses, defined
with a weight of 1 when the pulses are in their low states, and a
weight of +1 when they are in their high states.
The AD8134 and AD8146/AD8147/AD8148 data sheets contain
further details regarding the encoding scheme. Figure 20 illustrates
how the AD8123 comparators can be used to extract the horizontal
and vertical sync pulses that are encoded on the RGB common-
mode voltages by the aforementioned drivers.
USING THE VPEAK, VPOLE, VGAIN, AND VOFFSET INPUTS
The VPEAK input is the main peaking control and is used to
compensate for the low-pass roll-off in the cable response. The
VPOLE input is a secondary frequency response shaping control
that shifts the positions of the equalizer poles. The VGAIN input
controls the wideband flat gain and is used to compensate for
the low frequency cable loss that is nominally flat. The VOFFSET
input is used to produce an offset at the AD8123 output. The
output offset is equal to the voltage applied to the VOFFSET input,
limited by the output swing limits.
The VPEAK and VPOLE controls can be used independently or they
can be coupled to form a single peaking control. While Figure 17
and Figure 18 show recommended settings vs. cable length,
designers may find other combinations that they prefer. These
two controls give designers extra freedom, as well as the ability
to compensate for different cable types (such as UTP and coaxial
cable), as opposed to having only a single frequency shaping
control.
In some cases, as would likely be with automatic control, the
VPEAK control is derived from a low impedance source, such as
UTP application according to the recommended curves shown
source. Clearly, the 5 V supply must be clean to provide a clean
VPOLE voltage.
06
81
4-
02
6
VPEAK
2
+ 0.9V
20
5.11k
VPEAK
VPOLE ≈
5V
14k
8.25k
VPEAK
Figure 21. Deriving VPOLE from VPEAK with Low-Z Source for UTP Cable
The 20 Ω series resistor in the VPEAK path provides capacitive
load buffering for the op amp. This value can be modified,
depending on the actual capacitive load.
In automatic equalization circuits that place the control voltages
inside feedback loops, attention must be paid to the poles
produced by the summing resistors and load capacitances.
The peaking can also be adjusted by a mechanical or digitally
controlled potentiometer. In these cases, if the resistance of the
potentiometer is a couple of orders of magnitude lower than the
values of the resistors used to develop VPOLE, its resistance can be
ignored. Figure 22 shows how to use a 500 Ω potentiometer with
the resistor values shown in Figure 21 scaled up by a factor of 10.
068
14
-02
7
VPEAK
2
+ 0.9V
51.1k
VPEAK
VPOLE ≈
5V
140k
82.5k
750
500
Figure 22. Deriving VPOLE from VPEAK with Potentiometer for UTP Cable
Many potentiometers have wide tolerances. If a wide tolerance
potentiometer is used, it may be necessary to change the value
of the 750 Ω resistor to obtain a full swing for VPEAK.
The VGAIN input is essentially a contrast control and can be set
by adjusting it to produce the correct amplitude of a known test
signal (such as a white screen) at the AD8123 output.
VGAIN can also be derived from VPEAK according to the linear
how to derive VPOLE and VGAIN from VPEAK in a UTP application
that originates from a low-Z source.
0
68
14
-02
8
VPEAK
2
+ 0.9V
20
5.11k
VPEAK
VPOLE ≈
5V
14k
8.25k
5.11k
VGAIN ≈ 0.89 × VPEAK + 0.38V
5V
60.4k
133k
VPEAK
Figure 23. Deriving VPOLE and VGAIN from VPEAK with Low-Z Source for UTP Cable
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD8123ACPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with Adjustable Line Equalization |
| AD8123ACPZR2 | 制造商:Analog Devices 功能描述:Differential Receiver Amplifier 40-Pin LFCSP EP T/R |
| AD8123ACPZ-R2 | 制造商:Analog Devices 功能描述: |
| AD8123ACPZ-R7 | 功能描述:IC RCVR TRPL DIFF EQUAL 40LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 產(chǎn)品培訓模塊:RS-232 & USB Transceiver 標準包裝:2,000 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):1/1 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-SSOP（0.209"，5.30mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:296-19849-2 |
| AD8123ACPZ-R71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Triple Differential Receiver with Adjustable Line Equalization |
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