TA = 25°C, V
參數(shù)資料
型號(hào)： AD8120ACPZ-R2
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 10/16頁(yè)
文件大小： 0K
描述： IC ANLG VIDEO DELAY LINE 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類(lèi)型： 視頻延遲線
應(yīng)用： HD 視頻
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-LQFP
供應(yīng)商設(shè)備封裝： 32-LFCSP-EP（5x5）
包裝： 標(biāo)準(zhǔn)包裝
其它名稱(chēng)： AD8120ACPZ-R2DKR
Data Sheet
AD8120
Rev. A | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VS = ±5 V, RL = 150 , 10% to 90% input rise/fall time (tR/tF) = 4 ns, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DELAY CHARACTERISTICS
Total Adjustable Delay Range
Delay Code 63 to Delay Code 0
50
ns
Delay Resolution
Monotonic, 1 LSB
0.8
ns
Propagation Delay
Delay = 0 ns
4.9
ns
Channel-to-Channel Delay Error
All channels at maximum delay
0.4
ns
DYNAMIC PERFORMANCE
3 dB Video Signal Bandwidth
VOUT = 1.4 V p-p, delay = 0 ns
200
MHz
VOUT = 1.4 V p-p, delay = 50 ns
150
MHz
3 dB Small-Signal Bandwidth
VOUT = 0.2 V p-p, delay = 0 ns
165
MHz
VOUT = 0.2 V p-p, delay = 50 ns
140
MHz
0.1 dB Video Signal Flatness
VOUT = 1.4 V p-p, delay = 0 ns
27
MHz
VOUT = 1.4 V p-p, delay = 50 ns
35
MHz
10% to 90% Rise/Fall Time
VOUT = 1.4 V step, delay = 0 ns
2.5/3
ns
VOUT = 1.4 V step, delay = 50 ns
3/4.2
ns
Settling Time to 1%
VOUT = 1.4 V step, delay = 0 ns
8
ns
VOUT = 1.4 V step, delay = 50 ns
18
ns
Slew Rate
VOUT = 1.4 V step, delay = 0 ns, rising edge
550
V/μs
VOUT = 1.4 V step, delay = 0 ns, falling edge
540
V/μs
VOUT = 1.4 V step, delay = 50 ns, rising edge
510
V/μs
VOUT = 1.4 V step, delay = 50 ns, falling edge
360
V/μs
Overshoot
VOUT = 1.4 V step, delay = 0 ns
1
%
VOUT = 1.4 V step, delay = 50 ns
20
%
Gain
0 ns to 50 ns delay
1.95
2.01
2.06
V/V
Channel-to-Channel Gain Matching
Over all codes, among all channels
0.8
3
%
Hostile Crosstalk
Measured on G with R and B driven at 1 MHz,
VOUT = 1.4 V p-p, delay = 0 ns
80
dB
VIDEO INPUT CHARACTERISTICS
RIN, GIN, BIN
Input Bias Current
0.8
1.5
μA
Input Capacitance
1
pF
Input Resistance
500
k
VIDEO OUTPUT CHARACTERISTICS
ROUT, GOUT, BOUT
Output Voltage Swing
±3.25
V
Output Current
50
mA
Integrated Output Noise
100 kHz to 160 MHz
Delay = 0 ns
1
mV rms
Delay = 50 ns
4
mV rms
Output Offset Voltage (RTI)
Over all codes
30
0
+30
mV
Channel-to-Channel Output Offset Voltage
Matching (RTI)
Over all codes, among all channels
30
mV
Output Impedance
PD high, at 20 MHz
1.5
ANALOG CONTROL INPUT CHARACTERISTICS
Input Bias Current
VCR, VCG, VCB
1
μA
Operating Range
VCR, VCG, VCB
0
2
V
Delay Voltage Step Size in Linear Range
ΔVCR, ΔVCG, ΔVCB to move one delay LSB
28
mV
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