參數(shù)資料
型號: AD811
廠商: Analog Devices, Inc.
英文描述: High Performance Video Op Amp(高性能視頻運放)
中文描述: 高性能視頻運算放大器(高性能視頻運放)
文件頁數(shù): 13/16頁
文件大?。?/td> 286K
代理商: AD811
AD811
REV. C
–13–
A Video K eyer Circuit
By using two AD834 multipliers, an AD811, and a 1 V dc
source, a special form of a two-input VCA circuit called a
video keyer can be assembled. “K eying” is the term used in
reference to blending two or more video sources under the
control of a third signal or signals to create such special effects
as dissolves and overlays. T he circuit shown in Figure 41 is a
two-input keyer, with video inputs V
A
and V
B
, and a control
input V
G
. T he transfer function (with V
OUT
at the load) is
given by:
V
OUT
= G V
A
+ (1–G)
V
B
where G is a dimensionless variable (actually, just the gain of
the “A” signal path) that ranges from 0 when V
G
= 0, to 1
when V
G
= +1 V. T hus, V
OUT
varies continuously between V
A
and V
B
as G varies from 0 to 1.
Circuit operation is straightforward. Consider first the signal
path through U1, which handles video input V
A
. Its gain is
clearly zero when V
G
= 0 and the scaling we have chosen en-
sures that it is unity when V
G
= +1 V; this takes care of the
first term of the transfer function. On the other hand, the V
G
input to U2 is taken to the inverting input X 2 while X 1 is bi-
ased at an accurate +1 V. T hus, when V
G
= 0, the response to
video input V
B
is already at its full-scale value of unity,
whereas when V
G
= +1 V, the differential input X 1–X 2 is zero.
T his generates the second term.
T he bias currents required at the output of the multipliers are
provided by R8 and R9. A dc-level-shifting network comprising
R10/R12 and R11/R13 ensures that the input nodes of the
AD811 are positioned at a voltage within its common-mode
range. At high frequencies C1 and C2 bypass R10 and R11
respectively. R14 is included to lower the HF loop gain, and is
needed because the voltage-to-current conversion in the
AD834s, via the Y2 inputs, results in an effective value of the
feedback resistance of 250
; this is only about half the value
required for optimum flatness in the AD811’s response. (Note
that this resistance is unaffected by G: when G = 1, all the feed-
back is via U1, while when G = 0 it is all via U2). R14 reduces
the fractional amount of output current from the multipliers
into the current-summing inverting input of the AD811, by
sharing it with R8. T his resistor can be used to adjust the band-
width and damping factor to best suit the application.
T o generate the 1 V dc needed for the “1–G” term an AD589
reference supplies 1.225 V
±
25 mV to a voltage divider consist-
ing of resistors R2 through R4. Potentiometer R3 should be ad-
justed to provide exactly +1 V at the X 1 input.
In this case, we have shown an arrangement using dual supplies
of
±
5 V for both the AD834 and the AD811. Also, the overall
gain in this case is arranged to be unity at the load, when it is
driven from a reverse-terminated 75
line. T his means that the
“dual VCA” has to operate at a maximum gain of 2, rather
1
2
3
4
8
7
X1 +V
S
6
5
W1
X2
Y1
Y2
W2
–V
S
U1
AD834
7
6
4
3
2
U3
AD811
R8
29.4
R9
29.4
R12
6.98k
R13
6.98k
R10
C3
FB
V
OUT
FB
V
G
(0 TO +1V DC)
V
A
R6
226
R7
+5V
1
2
3
4
8
7
X1 +V
S
6
5
W1
X2
Y1
Y2
W2
–V
S
U1
AD834
–5V
+5V
U4
AD589
R5
113
(
±
1V FS)
–5V
R4
1.02k
R3
100
R2
174
R1
1.87k
V
B
(
±
1V FS)
+5V
–5V
C1
0.1μF
SER14
+5V
0.1μF
–5V
C4
0.1μF
C2
0.1μF
R11
LOAD
GND
LOAD
GND
Z
O
200
TO Y2
TO PIN 6
SETUP FOR DRIVING
REVERSE-TERMINATED LOAD
Z
O
200
V
OUT
INSET
Figure 41. A Practical Video Keyer Circuit
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