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參數(shù)資料
| 型號： | AD8113JSTZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO CROSSPOINT SWIT 100LQFP |
| 標準包裝： | 1 |
| 功能： | 音頻/視頻交叉點開關 |
| 電路： | 1 x 16:16 |
| 電壓電源： | 單/雙電源 |
| 電壓 - 電源，單路/雙路(±)： | 4.5 V ~ 5.5 V，±2.25 V ~ 6.3 V |
| 電流 - 電源： | 50mA |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應商設備封裝： | 100-LQFP（14x14） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 801 (CN2011-ZH PDF) |
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REV. A
AD8113
–15–
CALCULATION OF POWER DISSIPATION
AMBIENT TEMPERATURE – C
0
70
2.0
3.0
4.0
3.5
2.5
60
50
40
30
20
10
MAXIMUM
POWER
–
Watts
TJ = 150 C
Figure 6. Maximum Power Dissipation vs. Ambient
Temperature
The above curve was calculated from
P
TT
D MAX
NCTION MAX
AMBIENT
A
,
–
= ()
JU
J
θ
As an example, if the AD8113 is enclosed in an environment at
50
°C (TA), the total on-chip dissipation under all load and supply
conditions must not be allowed to exceed 2.5 W.
When calculating on-chip power dissipation, it is necessary to
include the rms current being delivered to the load, multiplied
by the rms voltage drop on the AD8113 output devices. The
dissipation of the on-chip, 4 k
feedback resistor network must
also be included. For a sinusoidal output, the on-chip power
dissipation due to the load and feedback network can be approxi-
mated by
PAV
V
I
V
k
DMAX
CC
OUTPUT RMS
,,
,
–
=
()×+
2
4
For nonsinusoidal output, the power dissipation should be cal-
culated by integrating the on-chip voltage drop multiplied by the
load current over one period.
The user may subtract the quiescent current for the Class AB
output stage when calculating the loaded power dissipation. For
each output stage driving a load, subtract a quiescent power
according to
PAV
AV
I
D OUTPUT
CC
EE
O QUIESCENT
,,
–
=
()×
For the AD8113, IO, QUIESCENT = 0.67 mA.
For each disabled output, the quiescent power supply current in
AVCC and AVEE drops by approximately 1.25 mA, although
there is a power dissipation in the on-chip feedback resistors if
the disabled output is being driven from an external source.
AGND
RF
4k
AVEE
IO, QUIESCENT
QPNP
VOUTPUT
IOUTPUT
QNPN
AVCC
IO, QUIESCENT
Figure 7. Simplified Output Stage
An example: AD8113, in an ambient temperature of 70
°C,
with all 16 outputs driving 6 V rms into 600
loads. Power
supplies are
±12 V.
Step 1. Calculate power dissipation of AD8113 using data sheet
quiescent currents.
PD, QUIESCENT = (AVCC
× IAVCC) + (AVEE × IAVEE) + (DVCC × IDVCC)
PD, QUIESCENT = (12 V
× 54 mA) + (–12 V × –54 mA)
+ (5 V
× 13 mA)
Step 2. Calculate power dissipation from loads.
PD, OUTPUT = (AVCC – VOUTPUT, RMS)
× I
OUTPUT, RMS
+ VOUTPUT
2/4k
PD, OUTPUT = (12 V – 6 V)
× 6 V/600 + (6 V)2/4 k = 69 mW
There are 16 outputs, so
nPD, OUTPUT = 16
× 69 mW = 1.1 W
Step 3. Subtract quiescent output current for number of loads
(assumes output voltage >> 0.5 V).
PDQ, OUTPUT = (AVCC – AVEE)
× I
O, QUIESCENT
PDQ, OUTPUT = (12 V – (–12 V))
× 0.67 mA = 16 mW
There are 16 outputs, so
nPD, OUTPUT = 16
× 16 mW = 0.3 W
Step 4. Verify that power dissipation does not exceed maximum
allowed value.
PD, ON-CHIP = PD, QUIESCENT + nPD, OUTPUT – nPDQ, OUTPUT
PD, ON-CHIP = 1.3 W + 1.1 W – 0.3 W = 2.1 W
From the figure or the equation, this power dissipation is below
the maximum allowed dissipation for all ambient temperatures
approaching 70
°C.
NOTE: It can be shown that for a dual supply of
±a, a Class AB
output stage dissipates maximum power into a grounded load
when the output voltage is a/2. So for a
± 12 V supply, the
above example demonstrates the worst-case power dissipation
into 600
. It can be seen from this example that the minimum
load resistance for
±12 V operation is 600 (for full rated oper-
ating temperature range). For larger safety margins, when the out-
put signal is unknown, loads of 1 k
and greater are recommended.
When operating with
±5 V supplies, this load resistance may be
lowered to 150
.
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