
AD8110/AD8111
–17–
REV. 0
T he basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to “wire-
OR” the outputs together in the vertical direction. T he meaning
of horizontal and vertical can best be understood by looking at
a diagram. Figure 42 illustrates this concept for a 32
×
8 cross-
point array.
AD8110
OR
AD8111
16
16
R
TERM
IN 00–15
AD8110
OR
AD8111
16
16
R
TERM
IN 16–31
8
8
Figure 42. A 32
×
8 Crosspoint Array Using Two AD8110s
or Two AD8111s
T he inputs are each uniquely assigned to each of the 32 inputs
of the two devices and terminated appropriately. T he outputs
are wire-ORed together in pairs. T he output from only one of a
wired OR pair should be enabled at any given time. T he device
programming software must be properly written to cause this to
happen.
16
R
TERM
IN 00–15
4
4
IN 16–31
IN 32–47
IN 48–63
IN 64–79
IN 80–95
IN 96–111
IN 112–127
4
4
4
4
RANK 2
16:8 NONBLOCKING
(16:16 BLOCKING)
RANK 1
(8 x AD8110)
128:16
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
16
R
TERM
4
4
AD8111
AD8110
AD8110
AD8110
AD8110
AD8110
AD8110
AD8110
AD8110
4
1k
V
4
1k
V
4
1k
V
4
1k
V
AD8111
OUT 00 – 07
NONBLOCKING
ADDITIONAL
8 OUTPUTS
(SUBJECT
TO BLOCKING)
Figure 43. A Gain-of-Two 128
×
8 Nonblocking Crosspoint Array (128
×
16 Blocking)
At some point, the number of outputs that are wire-ORed be-
comes too great to maintain system performance. T his will vary
according to which system specifications are most important. It
will also depend on whether the matrix consists of AD8110s or
AD8111s. T he output disabled impedance of the AD8110 is
much higher than that of the AD8111, so its disabled parasitics
will have a smaller effect on the one output that is enabled. For
example, a 128
×
8 crosspoint can be created with eight AD8110/
AD8111s. T his design will have 128 separate inputs and have
the corresponding outputs of each device wire-ORed together in
groups of eight.
Using additional crosspoint devices in the design can lower the
number of outputs that have to be wire-ORed together. Figure
43 shows a block diagram of a system using eight AD8110s and
two AD8111s to create a nonblocking, gain-of-two, 128
×
8
crosspoint that restricts the wire-ORing at the output to only
four outputs. T hese devices are the AD8110, which has a higher
disabled output impedance than the AD8111.
Additionally, by using the lower four outputs from each of the
two Rank 2 AD8111s, a blocking 128
×
16 crosspoint array can
be realized. T here are, however, some drawbacks to this tech-
nique. T he offset voltages of the various cascaded devices will
accumulate and the bandwidth limitations of the devices will
compound. In addition, the extra devices will consume more
current and take up more board space. Once again, the overall
system design specifications will determine how to make the
various tradeoffs.