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參數(shù)資料
| 型號： | AD809BRZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTH FREQ 155.52MHZ 16SOIC |
| 標準包裝： | 1,000 |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 無 |
| 輸入： | CMOS，ECL，PECL，TTL |
| 輸出： | ECL，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 155.52MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
AD809
REV. A
–5–
USING THE AD809
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10
F capacitor between V
CC and ground is recom-
mended. Care should be taken to isolate the +5 V power trace
to VCC2 (Pin 3). The VCC2 pin is used inside the device to pro-
vide the CLKOUT/CLKOUTN signals.
Use of a trace connecting Pin 14 and Pin 6 (AVCC2 and VCC1
respectively) is recommended. Use of 0.1
F capacitors between
IC power supply and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to the schematic, Figure 5, for advised connections.
Transmission Lines
Use of 50
transmission lines are recommended for PECL
inputs.
Terminations
Termination resistors should be used for PECL input signals.
Metal, thick film, 1% tolerance resistors are recommended.
Termination resistors for the PECL input signals should be
placed as close as possible to the PECL input pins.
Connections from the power supply to load resistors for input
and output signals should be individual, not daisy chained. This
will avoid crosstalk on these signals.
Loop Damping Capacitor, CD
A ceramic capacitor may be used for the loop damping capaci-
tor. A 22 nF capacitor provides a damping factor of 10.
Synthesizer Input
TTL/CMOSIN
Synthesizer Input
CLKIN/CLKINN
PECL INPUT
PLL Differential
Output Stage–
CLKOUT/CLKOUTN
2*ITTL
80A
OR
0A
2*ITTL
80A
OR
0A
500
VCC1
VEE
VCC2
DIFFERENTIAL
OUTPUT
VEE
2.6mA
460
460
500
7.5k
7.5k
ITTL
VCC1
VEE
500
40A
Figure 4. Simplified Schematics
VEE
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
VCC2
CLKOUTN
CLKOUT
CF1
CF2
MUX
CLKIN
CLKINN
AVCC1
TTL/CMOSIN
AVEE
GND
J5
MUX
EXT
+5V
AD809
16-PIN SOIC
SOLDERED TO BOARD
C1
0.1F
R6
3.65k
R5
301
R2
49.9
R1
49.9
JUMPER
W2
R16
301
VCC1
AVCC2
GUARD RING
+5V
GND
C11
10F
TP4
TP3
R7 100
R8 100
R12
154
R11
154
CD
TP1
TP2
C8
C7
C6
0.1F
R4
100
R3
100
VECTOR PINS SPACED FOR THROUGH-HOLE
CAPACITOR ON VECTOR CUPS.
COMPONENT SHOWN FOR REFERENCE ONLY.
C5 0.1F
J3
J4
C4 0.1F
ECL INN
ECL IN
CLKOUTN
CLKOUT
J2
C3 0.1F
J1
C2 0.1F
50
STRIP LINE
EQUAL LENGTH
JUMPER
W1
JUMPER
W3
R15
49.9
R14
49.9
J6
CLKIN
J7
CLKINN
C13 0.1F
C14 0.1F
J8
CMOS/TTL IN
C15 0.1F
R13
49.9
C12
0.1F
R17
3.65k
NOTE:
C7–C10 ARE 0.1F BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPx
TEST POINTS ARE VECTOR PINS
C9
C10
PECLINN
PECLIN
Figure 5. Evaluation Board Schematic
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