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參數(shù)資料
| 型號： | AD809 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 155.52 MHz Frequency Synthesizer(頻率合成器) |
| 中文描述： | 155.52兆赫頻率合成器（頻率合成器） |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 265K |
| 代理商： | AD809 |
AD809
REV. A
–5–
USING THE AD809
Ground Planes
Use of one ground plane for connections to both analog and
digital grounds is recommended.
Power Supply Connections
Use of a 10
μ
F capacitor between V
CC
and ground is recom-
mended. Care should be taken to isolate the +5 V power trace
to V
CC2
(Pin 3). The V
CC2
pin is used inside the device to pro-
vide the CLKOUT/CLKOUTN signals.
Use of a trace connecting Pin 14 and Pin 6 (AV
CC2
and V
CC1
respectively) is recommended. Use of 0.1
μ
F capacitors between
IC power supply and ground is recommended. Power supply
decoupling should take place as close to the IC as possible.
Refer to the schematic, Figure 5, for advised connections.
Transmission Lines
Use of 50
transmission lines are recommended for PECL
inputs.
Terminations
Termination resistors should be used for PECL input signals.
Metal, thick film, 1% tolerance resistors are recommended.
Termination resistors for the PECL input signals should be
placed as close as possible to the PECL input pins.
Connections from the power supply to load resistors for input
and output signals should be individual, not daisy chained. This
will avoid crosstalk on these signals.
Loop Damping Capacitor, C
D
A ceramic capacitor may be used for the loop damping capaci-
tor. A 22 nF capacitor provides a damping factor of 10.
Synthesizer Input
TTL/CMOSIN
Synthesizer Input
CLKIN/CLKINN
PECL INPUT
PLL Differential
Output Stage–
CLKOUT/CLKOUTN
2*I
TTL
80μA
OR
0μA
2*I
TTL
80μA
OR
0μA
500
V
CC1
V
EE
V
CC2
DIFFERENTIAL
OUTPUT
V
EE
2.6mA
460
460
500
7.5k
7.5k
I
TTL
V
CC1
V
EE
500
40μA
40μA
Figure 4. Simplified Schematics
V
EE
14
13
12
11
16
15
10
9
8
1
2
3
4
7
6
5
V
CC2
CLKOUTN
CLKOUT
CF1
CF2
MUX
CLKIN
CLKINN
AV
CC1
TTL/CMOSIN
AV
EE
GND
J5
MUX
EXT
+5V
AD809
16-PIN SOIC
SOLDERED TO BOARD
C1
0.1μF
R6
3.65k
R5
301
R2
49.9
R1
49.9
JUMPER
W2
R16
301
V
CC1
AV
CC2
GUARD RING
+5V
GND
C11
10μF
TP4
TP3
R7 100
R8 100
R12
154
R11
154
CD
TP1
TP2
C8
C7
C6
0.1μF
R4
100
R3
100
VECTOR PINS SPACED FOR THROUGH-HOLE
CAPACITOR ON VECTOR CUPS.
COMPONENT SHOWN FOR REFERENCE ONLY.
C5 0.1μF
J3
J4
C4 0.1μF
ECL INN
ECL IN
CLKOUTN
CLKOUT
J2
C3 0.1μF
J1
C2 0.1μF
50
STRIP LINE
EQUAL LENGTH
JUMPER
W1
JUMPER
W3
R15
49.9
R14
49.9
J6
CLKIN
J7
CLKINN
C13 0.1μF
C14 0.1μF
J8
CMOS/TTL IN
C15 0.1μF
R13
49.9
C12
0.1μF
R17
3.65k
NOTE:
C7–C10 ARE 0.1μF BYPASS CAPACITORS
RIGHT ANGLE SMA CONNECTOR
OUTER SHELL TO GND PLANE
ALL RESISTORS ARE 1% 1/8 WATT SURFACE MOUNT
TPx
C9
C10
PECLINN
PECLIN
Figure 5. Evaluation Board Schematic
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