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參數(shù)資料
| 型號： | AD8067ARTZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 8/25頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP VF R-R PREC LN SOT23-5 |
| 標準包裝： | 10,000 |
| 系列： | FastFET™ |
| 放大器類型： | 電壓反饋 |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 640 V/µs |
| -3db帶寬： | 54MHz |
| 電流 - 輸入偏壓： | 0.6pA |
| 電壓 - 輸入偏移： | 200µV |
| 電流 - 電源： | 6.6mA |
| 電流 - 輸出 / 通道： | 26mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 24 V，±2.5 V ~ 12 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SC-74A，SOT-753 |
| 供應商設備封裝： | SOT-23-5 |
| 包裝： | 帶卷 (TR) |
Data Sheet
AD8067
Rev. B | Page 15 of 24
DC ERROR CALCULATIONS
Figure 44 illustrates the primary dc errors associated with a
voltage feedback amplifier. For both inverting and noninverting
configurations:
+
=
G
F
G
OS
R
V
to
due
Error
Voltage
Output
F
B–
G
F
S
B
R
I
R
I
to
due
Error
Voltage
Output
×
+
×
=
+
–
Total error is the sum of the two.
DC common-mode and power supply effects can be added by
modeling the total VOS with the expression:
CMR
V
PSR
V
nom
V
tot
V
CM
S
OS
Δ
)
(
)
(
+
=
where:
VOS (nom) is the offset voltage specified at nominal conditions
(1 mV max).
VS is the change in power supply voltage from nominal
conditions.
PSR is power supply rejection (90 dB minimum).
VCM is the change in common-mode voltage from nominal test
conditions.
CMR is the common-mode rejection (85 dB minimum for the
AD8067).
VI
RS
RG
IB+
IB–
–
+
VOUT –
+
–
+
+VOS–
RF
Figure 44. Op Amp DC Error Sources
INPUT AND OUTPUT OVERLOAD BEHAVIOR
A simplified schematic of the AD8067 input stage is shown in
Figure 45. This shows the cascoded N-channel JFET input pair,
the ESD and other protection diodes, and the auxiliary NPN
input stage that eliminates phase inversion behavior.
When the common-mode input voltage to the amplifier is
driven to within approximately 3 V of the positive power
supply, the input JFET’s bias current turns off, and the bias of
the NPN pair turns on, taking over control of the amplifier. The
NPN differential pair now sets the amplifier’s offset, and the
input bias current is now in the range of several tens of
microamps. This behavior is illustrated in Figure 25 and Figure 26.
Normal operation resumes when the common-mode voltage
goes below the 3 V from the positive supply threshold.
The output transistors have circuitry included to limit the
extent of their saturation when the output is overdriven. This
improves output recovery time. A plot of the output recovery
time for the AD8067 used as a G = +10 buffer is shown in
VBIAS
VCC
VEE
VCC
VP
VN
SWITCH
CONTROL
VEE
VCC
TO REST OF AMP
VTHRESHOLD
Figure 45. Simplified Input Schematic
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| AD8067ARTZ-REEL7 | 功能描述:IC OPAMP VF R-R PREC LN SOT23-5 RoHS:是 類別:集成電路 (IC) >> Linear - Amplifiers - Instrumentation 系列:FastFET™ 產(chǎn)品培訓模塊:Differential Circuit Design Techniques for Communication Applications 標準包裝:1 系列:- 放大器類型:RF/IF 差分 電路數(shù):1 輸出類型:差分 轉(zhuǎn)換速率:9800 V/µs 增益帶寬積:- -3db帶寬:2.9GHz 電流 - 輸入偏壓:3µA 電壓 - 輸入偏移:- 電流 - 電源:40mA 電流 - 輸出 / 通道:- 電壓 - 電源，單路/雙路(±):3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VQFN 裸露焊盤，CSP 供應商設備封裝:16-LFCSP-VQ 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:551 (CN2011-ZH PDF) 其它名稱:ADL5561ACPZ-R7CT |
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