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參數(shù)資料
| 型號(hào)： | AD8037-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | MB 26C 26#20 PIN PLUG |
| 中文描述： | 低失真，寬帶電壓反饋鉗放大器 |
| 文件頁數(shù)： | 17/23頁 |
| 文件大小： | 387K |
| 代理商： | AD8037-EB |
AD8036/AD8037
REV. A
–17–
closed-loop gain at the output. For instance, to set an output
limit of
±
1 V for an AD8037 operating at a gain of 3.0, V
H
and
V
L
would need to be set to +0.333 V and –0.333 V, respectively.
The only restriction on using the AD8036’s and AD8037’s
+V
IN
, V
L
, V
H
pins as inputs is that the maximum voltage differ-
ence between +V
IN
and V
H
or V
L
should not exceed 6.3 V, and
all three voltages be within the supply voltage range. For ex-
ample, if V
L
is set at –3 V, then V
IN
should not exceed +3.3 V.
0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
INPUT VOLTAGE – +V
IN
1.6
0.6
1.2
0.8
1.0
1.4
O
O
AD8036
OUTPUT CLAMP AMP
CLAMP ERROR – 25mV
AD8036
CLAMP ERROR – >200mV
OUTPUT CLAMP
Figure 73. Output Clamp Error vs. Input Clamp Error
AD8036/AD8037 APPLICATIONS
The AD8036 and AD8037 use a unique input clamping circuit
to perform the clamping function. As a result, they provide the
clamping function better than traditional output clamping de-
vices and provide additional flexibility to perform other unique
applications.
There are, however, some restrictions on circuit configurations;
and some calculations need to be performed in order to figure
the clamping level, as a result of clamping being performed at
the input stage.
The major restriction on the clamping feature of the AD8036/
AD8037 is that clamping occurs only when using the amplifiers
in the noninverting mode. To clamp in an inverting circuit, an
additional inverting gain stage is required. Another restriction is
that V
H
be greater than V
L
, and that each be within the output
voltage range of the amplifier (
±
3.9 V). V
H
can go below ground
and V
L
can go above ground as long as V
H
is kept higher than V
L
.
Unity Gain Clamping
The simplest circuit for calculating the clamp levels is a unity
gain follower as shown in Figure 74. In this case, the AD8036
should be used since it is compensated for noninverting unity
gain.
This circuit will clamp at an upper voltage set by V
H
(the voltage
applied to Pin 8) and a lower voltage set by V
L
(the voltage ap-
plied to Pin 5).
Clamping with Gain
Figure 75 shows an AD8037 configured for a noninverting gain
of two. The AD8037 is used in this circuit since it is compen-
sated for gains of two or greater and provides greater band-
width. In this case, the high clamping level at the output will
+5V
R
F
140
V
–5V
130
V
V
H
V
L
V
IN
V
OUT
0.1
m
F
10
m
F
0.1
m
F
AD8036
0.1
m
F
10
m
F
V
H
0.1
m
F
V
L
Figure 74. Unity Gain Noninverting Clamp
occur at 2
×
V
H
and the low clamping level at the output will be
2
×
V
L
. The equations governing the output clamp levels in cir-
cuits configured for noninverting gain are:
V
CH
=
G
×
V
H
V
CL
=
G
×
V
L
where:
V
CH
is the high
output
clamping level
V
CL
is the low
output
clamping level
G is the gain of the amplifier configuration
V
H
is the high input clamping level (Pin 8)
V
L
is the low input clamping level (Pin 5)
*Amplifier offset is assumed to be zero.
+5V
R
F
274
V
–5V
100
V
V
H
V
L
V
IN
V
OUT
0.1
m
F
10
m
F
0.1
m
F
AD8037
0.1
m
F
10
m
F
V
H
0.1
m
F
V
L
R
G
274
V
49.9
V
Figure 75. Gain of Two Noninverting Clamp
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