參數(shù)資料
型號(hào)： AD8036AR
廠商： ANALOG DEVICES INC
元件分類(lèi)： 運(yùn)動(dòng)控制電子
英文描述： Low Distortion, Wide Bandwidth Voltage Feedback Clamp Amps
中文描述： OP-AMP, 11000 uV OFFSET-MAX, PDSO8
封裝： SOIC-8
文件頁(yè)數(shù)： 19/23頁(yè)
文件大小： 387K
代理商： AD8036AR
AD8036/AD8037
REV. A
–19–
The circuit uses an AD8037 operating at a gain of two with an
AD811 to boost the output to the
±
12 V range. The AD811 was
chosen for its ability to operate with
±
15 V supplies and its high
slew rate.
R1 and R2 act as a level shifter to make the TTL signal levels be
approximately symmetrical above and below ground. This en-
sures that both the high and low logic levels will be clamped by
the AD8037. For well controlled signal levels in the output
pulse, the high and low output levels should result from the
clamping action of the AD8037 and not be controlled by either
the high or low logic levels passing through a linear amplifier.
For good rise and fall times at the output pulse, a logic family
with high speed edges should be used.
The high logic levels are clamped at two times the voltage at V
H
,
while the low logic levels are clamped at two times the voltage
at V
L
. The output of the AD8037 is amplified by the AD811
operating at a gain of 5. The overall gain of 10 will cause the
high output level to be 10 times the voltage at V
H
, and the low
output level to be 10 times the voltage at V
L
.
High Speed, Full-Wave Rectifier
The clamping inputs are additional inputs to the input stage of
the op amp. As such they have an input bandwidth comparable
to the amplifier inputs and lend themselves to some unique
functions when they are driven dynamically.
Figure 78 is a schematic for a full-wave rectifier, sometimes
called an absolute value generator. It works well up to 20 MHz
and can operate at significantly higher frequencies with some
degradation in performance. The distortion performance is sig-
nificantly better than diode based full-wave rectifiers, especially
at high frequencies.
V
OUT
=
V
IN
+5V
R
F
274
V
–5V
100
V
V
H
V
L
V
IN
0.1
m
F
10
m
F
AD8037
0.1
m
F
10
m
F
R
G
274
V
Figure 78. Full-Wave Rectifier
TTL
IN
+15V
PULSE
OUT
V
H
3
10
V
L
3
10
–15V
+5V
274
V
–5V
100
V
V
H
V
L
0.1
m
F
10
m
F
0.1
m
F
AD8037
0.1
m
F
10
m
F
V
H
0.1
m
F
V
L
274
V
1.3k
V
200
V
100
V
AD811
–15V
0.1
m
F
10
m
F
0.1
m
F
10
m
F
604
V
150
V
Figure 77. Programmable Pulse Generator
The circuit is configured as an inverting amplifier with a gain
of one. The input drives the inverting amplifier and also directly
drives V
L
, the lower level clamping input. The high level clamp-
ing input, V
H
, is left floating and plays no role in this circuit.
When the input is negative, the amplifier acts as a regular unity-
gain inverting amplifier and outputs a positive signal at the same
amplitude as the input with opposite polarity. V
L
is driven nega-
tive by the input, so it performs no clamping action, because the
positive output signal is always higher than the negative level
driving V
L
.
When the input is positive, the output result is the sum of two
separate effects. First, the inverting amplifier multiplies the in-
put by –1 because of its unity-gain inverting configuration. This
effectively produces an offset as explained above, but with a dy-
namic level that is equal to –1 times the input.
Second, although the positive input is grounded (through 100
),
the output is clamped at two times the voltage applied to V
L
(a
positive, dynamic voltage in this case). The factor of two is be-
cause the noise gain of the amplifier is two.
The sum of these two actions results in an output that is equal
to unity times the input signal for positive input signals, see Fig-
ure 79. For a input/output scope photo with an input signal of
20 MHz and amplitude
±
1 V, see Figure 80.
INPUT
FULL WAVE
RECTIFIED
OUTPUT
LOWER
CLAMPING
LEVEL WITH
NO NEG INPUT
OUTPUT
LOWER
CLAMPING
LEVEL
–1
3
INPUT
Figure 79.
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