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參數(shù)資料
| 型號(hào)： | AD8036-EB |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 10/24頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL FOR AD8036 |
| 應(yīng)用說(shuō)明： | Using the Active Filter Design Tool, AN-649 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 每 IC 通道數(shù)： | 1 - 單 |
| 放大器類(lèi)型： | 電壓反饋 |
| 輸出類(lèi)型： | 單端 |
| 板類(lèi)型： | 裸（未填充） |
| 已供物品： | 板 |
| 已用 IC / 零件： | 8-SOIC 封裝 |
| 相關(guān)產(chǎn)品： | AD8036ANZ-ND - IC OPAMP VF ULDIST LN 70MA 8DIP AD8036ARZ-REEL7-ND - IC OPAMP VF ULDIST LN 70MA 8SOIC AD8036ARZ-REEL-ND - IC OPAMP VF ULDIST LN 70MA 8SOIC AD8036ARZ-ND - IC OPAMP VF ULDIST LN 70MA 8SOIC AD8036AR-REEL7-ND - IC OPAMP VF ULDIST LN 70MA 8SOIC AD8036AN-ND - IC OPAMP VF ULDIST LN 70MA 8DIP AD8036AR-ND - IC OPAMP VF ULDIST LN 70MA 8SOIC |
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AD8036/AD8037
REV. B
–17–
closed-loop gain at the output. For instance, to set an output
limit of
±1 V for an AD8037 operating at a gain of 3.0, V
H and
VL would need to be set to +0.333 V and –0.333 V, respectively.
The only restriction on using the AD8036’s and AD8037’s
+VIN, VL, VH pins as inputs is that the maximum voltage differ-
ence between +VIN and VH or VL should not exceed 6.3 V, and
all three voltages be within the supply voltage range. For example,
if VL is set at –3 V, then VIN should not exceed +3.3 V.
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
INPUT VOLTAGE – +VIN
1.6
0.6
1.2
0.8
1.0
1.4
OUTPUT
VOLTAGE
–
V
OUT
AD8036
OUTPUT CLAMP AMP
CLAMP ERROR – 25mV
AD8036
CLAMP ERROR – >200mV
OUTPUT CLAMP
Figure 7. Output Clamp Error vs. Input Clamp Error
AD8036/AD8037 APPLICATIONS
The AD8036 and AD8037 use a unique input clamping circuit
to perform the clamping function. As a result, they provide the
clamping function better than traditional output clamping
devices and provide additional flexibility to perform other
unique applications.
There are, however, some restrictions on circuit configurations;
and some calculations need to be performed in order to figure
the clamping level, as a result of clamping being performed at
the input stage.
The major restriction on the clamping feature of the AD8036/
AD8037 is that clamping occurs only when using the amplifiers
in the noninverting mode. To clamp in an inverting circuit, an
additional inverting gain stage is required. Another restriction is
that VH be greater than VL, and that each be within the output
voltage range of the amplifier (
±3.9 V). V
H can go below ground
and VL can go above ground as long as VH is kept higher than VL.
Unity Gain Clamping
The simplest circuit for calculating the clamp levels is a unity
gain follower as shown in Figure 8. In this case, the AD8036
should be used since it is compensated for noninverting unity gain.
This circuit will clamp at an upper voltage set by VH (the voltage
applied to Pin 8) and a lower voltage set by VL (the voltage
applied to Pin 5).
Clamping with Gain
Figure 9 shows an AD8037 configured for a noninverting gain
of two. The AD8037 is used in this circuit since it is compen-
sated for gains of two or greater and provides greater bandwidth.
In this case, the high clamping level at the output will occur at
+5V
RF
140
–5V
130
VH
VL
VIN
VOUT
0.1 F
10 F
0.1 F
AD8036
0.1 F10 F
VH
0.1 F
VL
Figure 8. Unity Gain Noninverting Clamp
2
× VH and the low clamping level at the output will be 2 × VL.
The equations governing the output clamp levels in circuits con-
figured for noninverting gain are:
VCH = G
× V
H
VCL = G
× V
L
where:
VCH is the high output clamping level
VCL is the low output clamping level
G is the gain of the amplifier configuration
VH is the high input clamping level (Pin 8)
VL is the low input clamping level (Pin 5)
*Amplifier offset is assumed to be zero.
+5V
RF
274
–5V
100
VH
VL
VIN
VOUT
0.1 F
10 F
0.1 F
AD8037
0.1 F10 F
VH
0.1 F
VL
RG
274
49.9
Figure 9. Gain of Two Noninverting Clamp
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