參數(shù)資料
型號(hào)： AD8033AKS-R2
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 13/25頁(yè)
文件大?。?/td> 0K
描述： IC OPAMP VF R-R LN LP SC70-5
標(biāo)準(zhǔn)包裝： 1
系列： FastFET™
放大器類型： 電壓反饋
電路數(shù)： 1
輸出類型： 滿擺幅
轉(zhuǎn)換速率： 80 V/µs
-3db帶寬： 80MHz
電流 - 輸入偏壓： 1.5pA
電壓 - 輸入偏移： 1000µV
電流 - 電源： 3.3mA
電流 - 輸出 / 通道： 60mA
電壓 - 電源，單路/雙路(±)： 5 V ~ 24 V，±2.5 V ~ 12 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 6-TSSOP（5 引線），SC-88A，SOT-353
供應(yīng)商設(shè)備封裝： SC-70-5
包裝： 剪切帶 (CT)
其它名稱： AD8033AKS-R2CT
AD8033/AD8034
Rev. D | Page 19 of 24
APPLICATIONS INFORMATION
HIGH SPEED PEAK DETECTOR
The low input bias current and high bandwidth of the AD8033/
AD8034 make the parts ideal for a fast settling, low leakage peak
detector. The classic fast-low leakage topology with a diode in
the output is limited to ~1.4 V p-p maximum in the case of the
AD8033/AD8034 because of the protection diodes across the
inputs, as shown in Figure 54.
AD8033/
AD8034
VIN
~1.4V p-p MAX
VOUT
02
92
4-
0
54
Figure 54. High Speed Peak Detector with Limited Input Range
Using the AD8033/AD8034, a unity gain peak detector can
be constructed that captures a 300 ns pulse while still taking
advantage of the low input bias current and wide common-
mode input range of the AD8033/AD8034, as shown in Figure 55.
Using two amplifiers, the difference between the peak and the
current input level is forced across R2 instead of either amplifier’s
input pins. In the event of a rising pulse, the first amplifier
compensates for the drop across D2 and D3, forcing the voltage
at Node 3 equal to Node 1. D1 is off and the voltage drop across
R2 is zero. Capacitor C3 speeds up the loop by providing the
charge required by the input capacitance of the first amplifier,
helping to maintain a minimal voltage drop across R2 in the
sampling mode. A negative going edge results in D2 and D3
turning off and D1 turning on, closing the loop around the
first amplifier and forcing VOUT VIN across R2. R4 makes
the voltage across D2 zero, minimizing leakage current and
kickback from D3 from affecting the voltage across C2.
The rate of the incoming edge must be limited so that the output
of the first amplifier does not overshoot the peak value of VIN
before the output of the second amplifier can provide negative
feedback at the summing junction of the first amplifier. This
is accomplished with the combination of R1 and C1, which
allows the voltage at Node 1 to settle to 0.1% of VIN in 270 ns.
The selection of C2 and R3 is made by considering droop
rate, settling time, and kickback. R3 prevents overshoot from
occurring at Node 3. The time constants of R1, C1 and R3, C2
are roughly equal to achieve the best performance. Slower time
constants can be selected by increasing C2 to minimize droop
rate and kickback at the cost of increased settling time. R1 and
C1 should also be increased to match, reducing the incoming
pulse’s effect on kickback.
AD8034
1/2
C3
10pF
R2
1k
R1
1k
AD8034
1/2
–VS
+VS
C1
39pF/
120pF
LS4148
VIN
R5
49.9
D1
4.7pF
C4
R4
6k
D3
LS4148
–VS
+VS
LS4148
R3
200
C2
180pF/
560pF
VOUT
D2
0
29
24
-0
56
Figure 55. High Speed, Unity Gain Peak Detector Using AD8034
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