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參數(shù)資料
| 型號： | AD8024ARZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/13頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CF QUAD LP 50MA 16SOIC |
| 標準包裝： | 1,000 |
| 放大器類型： | 電流反饋 |
| 電路數(shù)： | 4 |
| 轉換速率： | 390 V/µs |
| -3db帶寬： | 200MHz |
| 電流 - 輸入偏壓： | 1µA |
| 電壓 - 輸入偏移： | 2000µV |
| 電流 - 電源： | 16mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 5 V ~ 24 V，±2.5 V ~ 12 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-SOIC |
| 包裝： | 帶卷 (TR) |
AD8024
–10–
REV. C
Overload Recovery
The most important overload conditions are:
Input Common-Mode Voltage Overdrive
Output Voltage Overdrive
Input Current Overdrive.
When configured for a low closed-loop gain, the AD8024
recovers quickly from an input common-mode voltage over-
drive; typically in <25 ns.
When configured for a higher gain and overloaded at the output,
recovery from an output voltage overdrive is also short; approxi-
mately 55 ns (see Figure 5). For higher overdrive, the response
is somewhat slower. For 100% overdrive, the recovery time is
substantially longer.
When configured for a high noninverting gain, a high input over-
drive can result in a large current into the input stage. Although
this current is internally limited to approximately 30 mA, its
effect on the total power dissipation may be significant. See also
the warning under Maximum Power Dissipation.
VOUT
VIN
1V
5V
50ns
Figure 5. 15% Overload Recovery, Gain = +10
(RFB = 400
, RL = 1 k, VS = ±7.5 V)
Disable Mode Operation
When the Disable pin is tied to DGND, all amplifiers are opera-
tional, in the enabled state.
When the voltage on the Disable pin is raised to 1.6 V or more
above DGND, all amplifiers are in the disabled, powered-down
state. In this condition, the DISABLE pin sources approximately
0.1
A, the total quiescent current is reduced to approximately
500
A, all outputs are in a high impedance state, and there is a
high level of isolation from inputs to outputs.
The output impedance in the disabled mode is the equivalent of all
external resistors, seen from the output pin, in parallel with the
total disabled output impedance of the amplifier, typically 20 pF.
The input stages of the AD8024 include protection from large
differential input voltages that may be present in the disabled
mode. Internal clamps limit this voltage to 1.5 V. The high input-
to-output isolation is maintained for voltages below this limit.
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