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參數(shù)資料
| 型號： | AD8011-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 300 MHz, 1 mA Current Feedback Amplifier |
| 中文描述： | 300兆赫，1 mA電流反饋放大器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大小： | 219K |
| 代理商： | AD8011-EB |
AD8011
REV. B
–11–
1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09
FREQUENCY
–
Hz
400
370
340
310
280
220
190
250
R
–
20
P
–
0
–
20
–
40
–
120
160
130
100
–
140
–
160
–
180
–
60
–
80
–
100
SERIES 1
IMPEDANCE
Z
I
(s)
SERIES 2
PHASE
Figure 32. Open-Loop Inverting Input Impedance
Z
I
(s) goes positive real and approaches 1/2 g
mf
as
ω
approaches
(g
mc
×
R1
–
1)
/τ1
. This results in the input resistance for the
A
V
(s) complex term being 1/2 g
mf
; the parallel thermal emitter
resistances of Q3/Q4. Using the computed CLBW from A
V
(s)
above and the nominal design values for the other parameters,
results in a closed loop 3 dB BW equal to the open loop corner
frequency (1/2
πτ
1) times 1/[G/(2 g
mf
×
T
O
) + R
F
/T
O
]. For a
fixed R
F
, the 3 dB BW is controlled by the R
F
/T
O
term for low
gains and G/(2 g
mf
×
T
O
) for high gains. For example, using
nominal design parameters and R
1
= 1 k
(which results in a
nominal T
O
of 1.2 M
, the computed BW is 80 MHz for G = 0
(inverting I-V mode with R
N
removed) and 40 MHz for
G = +10/
–
9.
DRIVING CAPACITIVE LOADS
The AD8011 was designed primarily to drive nonreactive loads.
If driving loads with a capacitive component is desired, best
settling response is obtained by the addition of a small series
resistance as shown in Figure 33. The accompanying graph
shows the optimum value for R
SERIES
vs. capacitive load. It is
worth noting that the frequency response of the circuit when
driving large capacitive loads will be dominated by the passive
roll-off of R
SERIES
and C
L
.
1k
R
L
1k
C
L
R
SERIES
1k
AD8011
Figure 33. Driving Capacitive Load
where R1 is the input resistance to A2/A2B, and
τ1
(equal to
CD
×
R1
×
A2) is the open loop dominate time constant.
and T
O
(
s
)
=
|
A
2|
×
R
1
2
s
τ
1
+
1
1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09
FREQUENCY
–
Hz
140
120
100
80
60
20
0
40
G
–
0
P
–
–
40
–
80
–
120
–
160
–
200
–
240
–
280
PHASE
GAIN
T
O
(s)
Figure 31. Open-Loop Transimpedance Gain
Note that the ac open-loop plots in Figures 31, 32 and 33 are
based on the full Spice AD8011 simulations and do not include
external parasitics (see below). Nevertheless, these ac loop equa-
tions still provide a good approximation to simulated and actual
performance up to the CLBW of the amplifier. Typically g
mc
×
R1 is
–
4, resulting in A
O
(s) having a right half plane pole. In the
time domain (inverse Laplace of A
O
) it appears as unstable,
causing V
O
to exponentially rail out of its linear region. When
the loop is closed however, the BW is greatly extended and the
transimpedance gain, T
O
(s)
“
overrides
”
and directly controls
the amplifiers stability behavior due to Z
I
approaching 1/2 g
mf
for s>>1/
τ
1. See Figure 32. This can be seen by the Z
I
(s) and
A
V
(s) noninverting transfer equations below.
ZI
(
s
)
=
(1
–
gmc
×
R
1)
S
τ
1
1
–
gmc
×
R
1
+
1
2
×
gmf
(
S
τ
1
+
1)
A
V
(
s
)
=
G
1
+
G
A
O
+
R
F
T
O
S
τ
1
G
2
g
mf
T
O
+
R
F
T
O
+
1
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