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參數(shù)資料
| 型號： | AD7988-1BCPZ-RL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 23/24頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SRL 100KSPS 10LFCSP |
| 標準包裝： | 1,500 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 100k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤，CSP |
| 供應商設備封裝： | 10-LFCSP-WD（3x3） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個偽差分，單極 |
AD7988-1/AD7988-5
Data Sheet
Rev. D | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
10231-
004
AD7988-1/
AD7988-5
TOP VIEW
(Not to Scale)
Figure 4. 10-Lead MSOP Pin Configuration
NOTES
1. THE EXPOSED PAD CAN BE CONNECTED TO GND.
1
REF
2
VDD
3
IN+
4
IN–
5
GND
10 VIO
9
SDI
8
SCK
7
SDO
6
CNV
10231-
005
AD7988-1/
AD7988-5
TOP VIEW
(Not to Scale)
Figure 5. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The VREF range is from 2.4 V to 5.1 V. It is referred to the GND pin. The GND pin
should be decoupled closely to the REF pin with a 10 F capacitor.
2
VDD
P
Power Supply.
3
IN+
AI
Analog Input. It is referred to IN. The voltage range, for example, the difference between IN+ and IN, is
0 V to VREF.
4
IN
AI
Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
5
GND
P
Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when
CNV is low. In chain mode, the data should be read when CNV is high.
7
SDO
DO
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8
SCK
DI
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
EP
Exposed Pad. The exposed pad can be connected to GND.
1
AI = analog input, DI = digital input, DO = digital output, and P = power.
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