TA = 40°C to +85°C, VDD = 2.37 V to" />
參數(shù)資料
型號: AD7983BRMZ
廠商: Analog Devices Inc
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 1.33MSPS 10MSOP
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 1.33M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 管件
輸入數(shù)目和類型: 1 個差分,單極
產(chǎn)品目錄頁面: 780 (CN2011-ZH PDF)
AD7983
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
TA = 40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, unless otherwise noted. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
300
500
ns
Acquisition Time
tACQ
250
ns
Time Between Conversions
tCYC
750
ns
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
VIO Above 4.5 V
10.5
ns
VIO Above 3 V
12
ns
VIO Above 2.7 V
13
ns
VIO Above 2.3 V
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
11.5
ns
VIO Above 3 V
13
ns
VIO Above 2.7 V
14
ns
VIO Above 2.3 V
16
ns
SCK Low Time
tSCKL
4.5
ns
SCK High Time
tSCKH
4.5
ns
SCK Falling Edge to Data Remains Valid
tHSDO
3
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
9.5
ns
VIO Above 3 V
11
ns
VIO Above 2.7 V
12
ns
VIO Above 2.3 V
14
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 3 V
10
ns
VIO Above 2.3 V
15
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
20
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
2
ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
3
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
15
ns
500A
IOL
500A
IOH
1.4V
TO SDO
CL
20pF
06
97
4-
0
02
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
Y% VIO1
VIH2
VIL2
VIH2
tDELAY
1FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
06
97
4-
00
3
Figure 3. Voltage Levels for Timing
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