參數(shù)資料
型號: AD7983BCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 14/24頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 1.33MSPS 10LFCSP
標(biāo)準(zhǔn)包裝: 1
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 1.33M
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 12mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-WFDFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 10-LFCSP-WD(3x3)
包裝: 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型: 1 個差分,單極
其它名稱: AD7983BCPZ-RL7DKR
AD7983
Rev. A | Page 21 of 24
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7983s on a
3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7983s is shown in
Figure 34, and the corresponding timing is given in Figure 35.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7983 enters the acquisition phase and
goes into standby mode. The remaining data bits stored in the
internal shift register are clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first, and 16 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture the
data, a digital host using the SCK falling edge allows a faster
reading rate and, consequently, more AD7983s in the chain,
provided the digital host has an acceptable hold time. The
maximum conversion rate can be reduced due to the total
readback time.
DIGITAL HOST
CONVERT
CLK
DATA IN
AD7983 SDO
SDI
CNV
A
SCK
AD7983 SDO
SDI
CNV
B
SCK
06
97
4-
02
0
Figure 34. Chain Mode Without Busy Indicator Connection Diagram
tCONV
tCYC
tSSDISCK
tSCKL
tSCK
tHSDISCK
tACQ
ACQUISITION
tSSCKCNV
ACQUISITION
tSCKH
CONVERSION
SDOA = SDIB
tHSCKCNV
SCK
CNV
SDIA = 0
SDOB
tEN
DA15
DA14
DA13
DB15
DB14
DB13
DB1DB0DA15
DA14
DA0
DA1
DA1DA0
tHSDO
12
3
15
16
17
14
18
30
31
32
tDSDO
06
974
-02
1
Figure 35. Chain Mode Without Busy Indicator Serial Interface Timing
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