參數(shù)資料
型號： AD7952BCPZRL
廠商： Analog Devices Inc
文件頁數(shù)： 2/32頁
文件大?。?/td> 0K
描述： IC ADC 14BIT DIFF 1MSPS 48LFCSP
標準包裝： 2,500
系列： PulSAR®
位數(shù)： 14
采樣率（每秒）： 1M
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 260mW
電壓電源： 模擬和數(shù)字，雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 48-LFCSP-VQ（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個差分，雙極
AD7952
Data Sheet
Rev. A | Page 10 of 32
Pin No.
Mnemonic
Type1
Description
23
D8 or
DO
In parallel mode, this output is used as Bit 8 of the parallel port data output bus.
SYNC
Serial Data Frame Synchronization. In serial master mode (SER/PAR = high, EXT/INT= low), this
output is used as a digital output frame synchronization for use with the internal data clock.
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while
the SDOUT output is valid.
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while
the SDOUT output is valid.
24
D9 or
DO
In parallel mode, this output is used as Bit 9 of the parallel port data output bus.
RDERROR
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as
an incomplete data read error flag. If a data read is started and not completed when the current
conversion is completed, the current data is lost and RDERROR is pulsed high.
25
D10 or
DI/O
In parallel mode, this output is used as Bit 10 of the parallel port data output bus.
HW/SW
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure
the AD7952 by hardware or software. See the Hardware Configuration section and Software
When HW/SW = low, the AD7952 is configured through software using the serial configuration register.
When HW/SW = high, the AD7952 is configured through dedicated hardware input pins.
26
D11 or
DI/O
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
SCIN
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low),
this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
27
D12 or
DI/O
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
SCCLK
Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low), this
input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends
on the logic state of the INVSCLK pin. See the Software Configuration section.
28
D13 or
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
SCCS
Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low),
this input enables the serial configuration port. See the Software Configuration section.
29
BUSY
DO
Busy Output. Transitions high when a conversion is started and remains high until the conversion
is completed and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data-ready clock signal. Note that in master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC = low), the busy time changes according to Table 4.
30
TEN
DI2
Input Range Select. Used in conjunction with BIPOLAR per the following.
Input Range (V)
BIPOLAR
TEN
0 to 5
Low
0 to 10
Low
High
±5
High
Low
±10
High
31
RD
DI
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS
is also used to gate the external clock in slave serial mode (not used for serial configurable port).
33
RESET
DI
Reset Input. When high, reset the AD7952. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zeros (with OB/2C = high) and clears the configuration register.
See the Digital Interface section. If not used, this pin can be tied to OGND.
34
PD
DI2
Power-Down Input. When PD = high, powers down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power-down.
35
CNVST
DI
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
36
BIPOLAR
DI2
Input Range Select. See description for Pin 30.
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