
Data Sheet
AD7949
Rev. D | Page 7 of 32
VDD = 2.3 V to 4.5 V, VIO = 1.8 V to VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
3.2
s
Acquisition Time
tACQ
1.8
s
Time Between Conversions
tCYC
5
s
Data Write/Read During Conversion
tDATA
1.2
s
CNV Pulse Width
tCNVH
10
ns
SCK Period
tSCK
tDSDO + 2
ns
SCK Low Time
tSCKL
12
ns
SCK High Time
tSCKH
12
ns
SCK Falling Edge to Data Remains Valid
tHSDO
5
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 3 V
24
ns
VIO Above 2.7 V
30
ns
VIO Above 2.3 V
38
ns
VIO Above 1.8 V
48
ns
CNV Low to SDO D15 MSB Valid
tEN
VIO Above 3 V
21
ns
VIO Above 2.7 V
27
ns
VIO Above 2.3 V
35
ns
VIO Above 1.8 V
45
ns
CNV High or Last SCK Falling Edge to SDO High Impedance
tDIS
50
ns
CNV Low to SCK Rising Edge
tCLSCK
10
ns
DIN Valid Setup Time from SCK Rising Edge
tSDIN
5
ns
DIN Valid Hold Time from SCK Rising Edge
tHDIN
5
ns
1
IOL
500A
IOH
1.4V
TO SDO
CL
50pF
07351-
002
Figure 2. Load Circuit for Digital Interface Timing
30% VIO
70% VIO
2V OR VIO – 0.5V1
0.8V OR 0.5V2
2V OR VIO – 0.5V1
tDELAY
1 2V IF VIO ABOVE 2.5V, VIO – 0.5V IF VIO BELOW 2.5V.
2 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
07351-
003
Figure 3. Voltage Levels for Timing