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| 型號(hào)： | AD7948ARS-B |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 12BIT MULT PARALL 20-SSOP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 設(shè)置時(shí)間： | 600ns |
| 位數(shù)： | 12 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 單電源 |
| 功率耗散（最大）： | 25µW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 輸出數(shù)目和類(lèi)型： | 1 電流，單極；1 電流，雙極 |
| 采樣率（每秒）： | 1.7M |
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AD7943/AD7945/AD7948
REV. B
–13–
GENERAL DESCRIPTION
D/A Section
The AD7943, AD7945 and AD7948 are 12-bit current-output
D/A converters. A simplified circuit diagram is shown in Fig-
ure 13. The DAC architecture is segmented. This means that
the 2 MSBs of the 12-bit data word are decoded to drive the
three switches A, B and C. The remaining 10 bits of the data
word drive the switches S0 to S9 in a standard inverting R-2R
ladder configuration.
Each of the switches A to C steers 1/4 of the total reference
current into either IOUT1 or IOUT2 with the remaining 1/4 of the
total current passing through the R-2R section. Switches S9 to
S0 steer binarily weighted currents into either IOUT1 or IOUT2. If
IOUT1 and IOUT2 are kept at the same potential, a constant cur-
rent flows in each ladder leg, regardless of digital input code.
Thus, the input resistance seen at VREF is always constant. It is
equal to R/2. The VREF input may be driven by any reference
voltage or current, ac or dc that is within the Absolute Maxi-
mum Ratings.
The device provides access to the VREF, RFB, and IOUT1 termi-
nals of the DAC. This makes the device extremely versatile and
allows it to be configured in several different operating modes.
Examples of these are shown in the following sections. The
AD7943 also has a separate IOUT2 pin. In the AD7945 and
AD7948 this is internally tied to AGND.
When an output amplifier is connected in the standard configu-
ration of Figure 14, the output voltage is given by:
VOUT = –D
× V
REF
where D is the fractional representation of the digital word
loaded to the DAC. D can be set from 0 to 4095/4096, since it
has 12-bit resolution.
VREF
2R
R/2
RR
R
CA
BS9
S8
S0
RFB
IOUT1
IOUT2
2R
SHOWN FOR ALL 1S ON DAC
Figure 13. Simplified D/A Circuit Diagram
UNIPOLAR BINARY OPERATION
(Two-Quadrant Multiplication)
Figure 14 shows the standard unipolar binary connection dia-
gram for the AD7943, AD7945 and AD7948. When VIN is an
ac signal, the circuit performs two-quadrant multiplication.
Resistors R1 and R2 allow the user to adjust the DAC gain
error. With a specified gain error of 2 LSBs over temperature,
these are not necessary in many applications. Circuit offset is
due completely to the output amplifier offset. It can be re-
moved by adjusting the amplifier offset voltage. Alternatively,
choosing a low offset amplifier makes this unnecessary.
A1 should be chosen to suit the application. For example, the
OP07 is ideal for very low bandwidth applications (10 kHz or
IOUT1
IOUT2
A1
VOUT
SIGNAL GROUND
A1: OP07
AD711
AD843
AD845
AGND
DAC
VREF
R1 20
AD7943/45/48
VIN
R2 10
RFB
C1
NOTES
1. ONLY ONE DAC IS SHOWN FOR CLAIRITY.
2. DIGITAL INPUT CONNECTIONS ARE OMITTED.
3. C1 PHASE COMPENSATION (5 – 15pF) MAY BE REQUIRED
WHEN USING HIGH SPEED AMPLIFIER.
Figure 14. Unipolar Binary Operation
lower) while the AD711 is suitable for medium bandwidth ap-
plications (200 kHz or lower). For high bandwidth applications
of greater than 200 kHz, the AD843 and AD847 offer very fast
settling times.
The code table for Figure 14 is shown in Table III.
Table III. Unipolar Binary Code
Digital Input
Analog Output
MSB
LSB
(VOUT as Shown in Figure 14)
1111 1111 1111
–VREF (4095/4096)
1000 0000 0001
–VREF (2049/4096)
1000 0000 0000
–VREF (2048/4096)
0111 1111 1111
–VREF (2047/4096)
0000 0000 0001
–VREF (1/4096)
0000 0000 0000
–VREF (0/4096) = 0
NOTE
Nominal LSB size for the circuit of Figure 14 is given by: V REF (1/4096).
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