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參數(shù)資料
| 型號(hào)： | AD7944BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 10/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 2.5MSPS 20LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | PulSAR® |
| 位數(shù)： | 14 |
| 采樣率（每秒）： | 2.5M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 33mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 20-LFCSP-VQ |
| 包裝： | 托盤 |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，單極 |
| 產(chǎn)品目錄頁面： | 780 (CN2011-ZH PDF) |
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AD7944
Rev. A | Page 18 of 28
DATA READING OPTIONS
There are three different data reading options for the AD7944.
There is the option to read during conversion, to split the read
across acquisition and conversion (see Figure 28 and Figure 29),
and, in normal mode, to read during acquisition. The desired
SCK frequency largely determines the reading option to use.
Reading During Conversion, Fast Host (Turbo or
Normal Mode)
When reading during conversion (n), conversion results are for
the previous (n 1) conversion. Reading should occur only up
to tDATA and, because this time is limited, the host must use a
fast SCK.
The required SCK frequency is calculated by
DATA
SCK
t
Edges
SCK
Number
f
_
≥
To determine the minimum SCK frequency, follow these
examples to read data from conversion (n 1).
For turbo mode (2.5 MSPS)
Number_SCK_Edges = 14; tDATA = 190 ns
fSCK = 14/190 ns = 73.7 MHz
For normal mode (2.0 MSPS)
Number_SCK_Edges = 14; tDATA = 290 ns
fSCK = 14/290 ns = 48.3 MHz
The time between tDATA and tCONV is an I/O quiet time during
which digital activity should not occur, or sensitive bit decisions
may be corrupted.
Split Reading, Any Speed Host (Turbo or Normal Mode)
To allow for a slower SCK, there is the option of a split read,
where data access starts at the current acquisition (n) and spans
into the conversion (n). Conversion results are for the previous
(n 1) conversion.
Similar to reading during conversion, split reading should
occur only up to tDATA. For the maximum throughput, the
only time restriction is that split reading take place during the
tACQ (minimum) + (tDATA tQUIET) time. The time between the
falling edge of SCK and CNV rising is an acquisition quiet
time, tQUIET.
To determine how to split the read for a particular SCK frequency,
follow these examples to read data from conversion (n 1).
For turbo mode (2.5 MSPS)
fSCK = 50 MHz; tDATA = 190 ns
Number_SCK_Edges = 50 MHz × 190 ns = 9.5
Nine bits are read during conversion (n), and five bits are read
during acquisition (n).
For normal mode (2.0 MSPS)
fSCK = 40 MHz; tDATA = 290 ns
Number_SCK_Edges = 40 MHz × 290 ns = 11.6
Eleven bits are read during conversion (n), and three bits are
read during acquisition (n).
For slow throughputs, the time restriction is dictated by the
throughput required by the user; the host is free to run at any
speed. Similar to reading during acquisition, data access for
slow hosts must take place during the acquisition phase with
additional time into the conversion.
Note that data access spanning conversion requires the CNV
pin to be driven high to initiate a new conversion, and data
access is not allowed when CNV is high. Thus, the host must
perform two bursts of data access when using this method.
Reading During Acquisition, Any Speed Host (Turbo or
Normal Mode)
When reading during acquisition (n), conversion results are
for the previous (n 1) conversion. Maximum throughput is
achievable in normal mode (2.0 MSPS); however, in turbo
mode, 2.5 MSPS throughput is not achievable.
For the maximum throughput, the only time restriction is that
reading take place during the tACQ (minimum) time. For slow
throughputs, the time restriction is dictated by the throughput
required by the user; the host is free to run at any speed. Thus,
for slow hosts, data access must take place during the acquisi-
tion phase.
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| AD7944BCPZ-RL7 | 功能描述:IC ADC 14B 2.5MSPS PULSR 20LFCSP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:PulSAR® 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
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| AD7945AN-B | 功能描述:IC DAC 12BIT MULT PARALL 20-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:2,400 系列:- 設(shè)置時(shí)間:- 位數(shù):18 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:3 電壓電源:模擬和數(shù)字 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:36-TFBGA 供應(yīng)商設(shè)備封裝:36-TFBGA 包裝:帶卷 (TR) 輸出數(shù)目和類型:* 采樣率（每秒）:* |
| AD7945ANZ-B | 功能描述:IC DAC 12BIT MULT PARALL 20DIP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:47 系列:- 設(shè)置時(shí)間:2µs 位數(shù):14 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:55µW 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:管件 輸出數(shù)目和類型:1 電流，單極；1 電流，雙極 采樣率（每秒）:* |
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