參數(shù)資料
型號: AD7921AUJZ-REEL7
廠商: Analog Devices Inc
文件頁數(shù): 13/28頁
文件大?。?/td> 0K
描述: IC ADC 12BIT DUAL LP TSOT-23-8
標準包裝: 1
位數(shù): 12
采樣率(每秒): 250k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉換器數(shù)目: 1
功率耗散(最大): 20mW
電壓電源: 單電源
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: SOT-23-8 薄型,TSOT-23-8
供應商設備封裝: TSOT-23-8
包裝: 標準包裝
輸入數(shù)目和類型: 2 個單端,單極
其它名稱: AD7921AUJZ-REEL7DKR
AD7911/AD7921
Rev. A | Page 20 of 28
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7911/AD7921 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 29 shows how, as the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over
time drops accordingly.
For example, if the AD7911/AD7921 are operating in a
continuous sampling mode with a throughput rate of 50 kSPS
and a SCLK of 5 MHz (VDD = 5 V) and the devices are placed in
power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 20 mW (VDD = 5 V). If one dummy
cycle powers up the part between conversions (3.2 μs), and the
remaining conversion time is another cycle (3.2 μs), then the
AD7911/AD7921 dissipate 20 mW for 6.4 μs during each
conversion cycle. If the throughput rate is 50 kSPS and the cycle
time is 20 μs, then the average power dissipated during each
cycle is
(6.4/20) × (20 mW) = 6.4 mW
If VDD = 3 V, SCLK= 5 MHz, and the device is again in power-
down mode between conversions, then the power dissipation
during normal operation is 6 mW. The AD7911/AD7921 now
dissipate 6 mW for 6.4 μs during each conversion cycle. With a
throughput rate of 50 kSPS, the average power dissipated during
each cycle is
(6.4/20) × (6 mW) = 1.92 mW
In the previous examples, the power dissipation when the part
is in power-down mode has not been taken into account,
because the shutdown current is so low that it does not have any
effect on the overall power dissipation value. Figure 29 shows
the power consumption versus throughput rate when using the
power-down mode between conversions with both 5 V and 3 V
supplies.
Power-down mode is intended for use with throughput rates of
approximately 120 kSPS and under, because higher sampling
rates do not have a power saving in power-down mode.
0.01
100
10
1
0.1
0
135
120
105
90
75
60
45
30
15
04350-0-035
THROUGHPUT (kSPS)
P
O
WE
R
(mW)
VDD = 5V, SCLK = 5MHz
VDD = 3V, SCLK = 5MHz
Figure 29. Power Consumption vs. Throughput Rate
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