參數(shù)資料
型號(hào): AD790SQ
廠商: Analog Devices Inc
文件頁(yè)數(shù): 6/12頁(yè)
文件大小: 0K
描述: IC COMPARATOR PREC W/LATCH 8CDIP
設(shè)計(jì)資源: Automated Calibration Technique That Reduces AD5360 Offset Voltage to Less Than 1 mV (CN0123)
標(biāo)準(zhǔn)包裝: 1
類型: 帶鎖銷
元件數(shù): 1
輸出類型: CMOS,TTL
電壓 - 電源,單路/雙路(±): 4.5 V ~ 7 V,±2.25 V ~ 16.5 V
電壓 - 輸入偏移(最小值): 1.5mV @ 5V
電流 - 輸入偏壓(最小值): 5µA @ 5V
電流 - 靜態(tài)(最大值): 10mA
CMRR, PSRR(標(biāo)準(zhǔn)): 95dB CMRR,90dB PSRR
傳輸延遲(最大): 50ns
磁滯: 500µV
工作溫度: -55°C ~ 125°C
封裝/外殼: 8-CDIP(0.300",7.62mm)
安裝類型: 通孔
包裝: 管件
SINGLE SUPPLY
AD790J/A
AD790K/B
AD790S
Parameter
Conditions
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
RESPONSE CHARACTERISTIC
100 mV Step
Propagation Delay, tPD
5 mV Overdrive
45
50
45
50
45
50
ns
TMIN to TMAX
50/60
65
ns
OUTPUT CHARACTERISTICS
Output HIGH Voltage, VOH
1.6 mA Source
4.65
6.4 mA Source
4.3
4.45
4.3
4.45
4.3
4.45
V
TMIN to TMAX
4.3
4.3
V
Output LOW Voltage, VOL
1.6 mA Sink
0.35
V
6.4 mA Sink
0.44
0.5
0.44
0.5
0.44
0.5
V
TMIN to TMAX
0.5
0.5
V
INPUT CHARACTERISTICS
Offset Voltage
2
0.45
1.5
0.35
0.6
0.45
1.5
mV
TMIN to TMAX
2.0
0.85
2.0
mV
Hysteresis
3
TMIN to TMAX
0.3
0.5
0.75
0.3
0.5
0.65
0.3
0.7
1.0
mV
Bias Current
Either Input
2.7
5
2.0
3.5
2.7
5
A
TMIN to TMAX
7
58
A
Offset Current
0.04
0.25
0.02
0.15
0.04
0.25
A
TMIN to TMAX
0.3
0.2
0.4
A
Power Supply
Rejection Ratio DC
4.5 V
≤V
S
≤5.5 V
80
90
86
100
80
90
dB
TMIN to TMAX
76/76 88
82
93
76
85
dB
Input Voltage Range
Differential Voltage
VS
V
Common Mode
0
+VS–2 V
0
+VS–2 V
0
+VS–2 V V
Input Impedance
20 220 220 2M
pF
LATCH CHARACTERISTICS
Latch Hold Time, tH
25
35
25
35
25
35
ns
Latch Setup Time, tS
510
5
10
510
ns
LOW Input Level, VIL
TMIN to TMAX
0.8
0.8
V
HIGH Input Level, VIH
TMIN to TMAX
1.6
1.6
V
Latch Input Current
2.3
5
2.3
3.5
2.3
5
A
TMIN to TMAX
7
58
A
SUPPLY CHARACTERISTICS
Supply Voltage
4
TMIN to TMAX
4.5
7
4.5
7
4.7
7
V
Quiescent Current
10
12
10
12
10
12
mA
Power Dissipation
60
mW
TEMPERATURE RANGE
Rated Performance
TMIN to TMAX
0 to 70/–40 to +85
–55 to +125
°C
NOTES
1Pin 1 tied to Pin 8, and Pin 4 tied to Pin 6.
2Defined as the average of the input voltages at the low to high and high to low transition points. Refer to Figure 6.
3Defined as half the magnitude between the input voltages at the low to high and high to low transition points. Refer to Figure 6.
4–V
S must not be connected above ground.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units at final test.
Specifications subject to change without notice.
AD790
REV. D
–3–
(Operation @ 25 C and +VS = VLOGIC = 5 V, –VS = 0 V unless otherwise noted.)
1
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