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| 型號(hào)： | AD7884APZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 2/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SAMPLING HS 44PLCC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 166k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 325mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC（16.59x16.59） |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 1 個(gè)差分，雙極 |
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REV. E
AD7884/AD7885
–10–
USING THE AD7884/AD7885 ANALOG INPUT RANGES
The AD7884/AD7885 can be set up to have either a
±3 V analog
input range or a
±5 V analog input range. Figures 10 and 11 show
the necessary corrections for each of these. The output code is
twos complement and the ideal code table for both input ranges
is shown in Table I.
Reference Considerations
The AD7884/AD7885 operates from a
±3 V reference. This can
be derived simply using the AD780 as shown in Figure 6.
5VINS
5VINF
3VINS
3VINF
VINV
A1
Figure 10.
±5 V Input Range Connection
3VINS
3VINF
5VINS
5VINF
VINV
A1
Figure 11.
±3 V Input Range Connections
The critical performance specification for a reference in a 16-bit
application is noise. The reference peak-to-peak noise should be
insignificant in comparison to the ADC noise. The AD7884/AD7885
has a typical rms noise of 120
V. For example, a reasonable
target would be to keep the total rms noise less than 125
V.
To do this the reference noise needs to be less than 35
V rms.
In the 100 kHz band, the AD780 noise is less than 30
V rms,
making it a very suitable reference.
The buffer amplifier used to drive the device VREF+ should have
low enough noise performance so as not to affect the overall
system noise requirement. The AD845 and AD817 achieve this.
Decoupling and Grounding
The AD7884 and AD7885A have one AVDD pin and two VDD
pins. They also have one AVSS pin and three VSS pins. The
AD7885 has one AVDD pin, one VDD pin, one AVSS pin, and
one VSS pin. Figure 6 shows how a common +5 V supply should
be used for the positive supply pins and a common –5 V supply
for the negative supply pins.
For decoupling purposes, the critical pins on both devices are
the AVDD and AVSS pins. Each of these should be decoupled to
system AGND with 10
F tantalum and 0.1 F ceramic capaci-
tors right at the pins. With the VDD and VSS pins, it is sufficient
to decouple each of these with ceramic 1
F capacitors.
AGNDS, AGNDF are the ground return points for the on-chip
9-bit ADC. They should be driven by a buffer amplifier as shown
in Figure 6. If they are tied directly together and then to ground,
there will be a marginal degradation in linearity performance.
The GND pin is the analog ground return for the on-chip lin-
ear circuitry. It should be connected to system analog ground.
The DGND pin is the ground return for the on-chip digital
circuitry. It should be connected to the ground terminal of the
VDD and VSS supplies. If a common analog supply is used for
AVDD and VDD, then DGND should be connected to the com-
mon ground point.
Power Supply Sequencing
AVDD and VDD are connected to a common substrate and there is
typically 17
resistance between them. If they are powered by
separate 5 V supplies, then these should come up simultaneously.
Otherwise, the one that comes up first will have to drive 5 V
into a 17
load for a short period of time. However, the standard
short-circuit protection on regulators like the 7800 series will
ensure that there is no possibility of damage to the driving device.
AVSS should always come up either before or at the same
time as VSS. If this cannot be guaranteed, Schottky diodes
should be used to ensure that VSS never exceeds AVSS by
more than 0.3 V. Arranging the power supplies as in Figure 6
and using the recommended decoupling ensures that there
are no power supply sequencing issues as well as giving the
specified noise performance.
AVDD
VDD
AVSS
VSS
+5V
–5V
AD7884/AD7885
HP5082-2810
OR
EQUIVALENT
Figure 12. Schottky Diodes Used to Protect Against
Incorrect Power Supply Sequencing
Analog Input
3 V
5 V
Digital Output
In Terms of FSR
2 Range3
Range
4
Code Transition
l
+FSR/2 – 1 LSB
2.999908
4.999847
011 . . . 111 to 111 . . . 110
+FSR/2 – 2 LSBs
2.999817
4.999695
011 . . . 110 to 011 . . . 101
+FSR/2 – 3 LSBs
2.999726
4.999543
011 . . . 101 to 011 . . . 100
AGND + 1 LSB
0.000092
0.000153
000 . . . 001 to 000 . . . 000
AGND
0.000000
000 . . . 000 to 111 . . . 111
AGND – 1 LSB
–0.000092
–0.000153
111 . . . 111 to 111 . . . 110
–(FSR/2 – 3 LSBs)
–2.999726
–4.999543
100 . . . 011 to 100 . . . 010
–(FSR/2 – 2 LSBs)
–2.999817
–4.999695
100 . . . 010 to 100 . . . 001
–(FSR/2 – 1 LSB)
–2.999908
–4.999847
100 . . . 001 to 100 . . . 000
NOTES
1This table applies for V
REF+S = 3 V.
2FSR (full-scale range) is 6 V for the
±3 V input range and 10 V for the
±5 V input range.
31 LSB on the
±3 V range is FSR/216 and is equal to 91.5 V.
41 LSB on the
± 5 V range is FSR/216 and is equal to 152.6 V.
Table I. Ideal Output Code Table for the AD7884/AD7885
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