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參數(shù)資料
型號: AD7879-1WARUZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 37/41頁
文件大?。?/td> 0K
描述: IC ADC 12BIT CTRLR TOUCH 16TSSOP
標準包裝: 2,500
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
評估套件: *
數(shù)據(jù)接口: I²C,串行
數(shù)據(jù)速率/采樣率 (SPS,BPS): 105k
電壓基準: 內(nèi)部
電源電壓: 1.6 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 16-TSSOP
包裝: 帶卷 (TR)
AD7879/AD7889
Rev. C | Page 4 of 40
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VCC
1.6
2.6
3.6
V
Specified performance.
ICC
Digital inputs = 0 V or VCC.
Converting Mode
480
650
A
ADC on, PM = 10.
Static
406
A
ADC and temperature sensor are off; the
reference and oscillator are on; PM = 01
or 11.
Shutdown Mode
0.5
6
A
PM = 00.
1
See the Terminology section.
2
Guaranteed by characterization; not production tested.
3
Sample tested at 25°C to ensure compliance.
SPI TIMING SPECIFICATIONS (AD7879/AD7889)
VCC = 1.6 V to 3.6 V, TA = 40°C to +85°C, unless otherwise noted. Sample tested at 25°C to ensure compliance. All input signals are
specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.4 V.
Table 2.
Parameter1
Limit
Unit
Description
fSCL
5
MHz max
t1
5
ns min
CS falling edge to first SCL falling edge
t2
20
ns min
SCL high pulse width
t3
20
ns min
SCL low pulse width
t4
15
ns min
DIN setup time
t5
15
ns min
DIN hold time
t6
20
ns max
DOUT access time after SCL falling edge
t7
16
ns max
CS rising edge to DOUT high impedance
t8
15
ns min
SCL rising edge to CS high
1
Guaranteed by design; not production tested.
CS
SCL
DIN
DOUT
t1
1
16
15
MSB
LSB
2
3
MSB
LSB
1
2
15
16
t2
t4
t5
t3
t6
t7
t8
07667-
002
Figure 2. Detailed SPI Timing Diagram
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